| /onnv/onnv-gate/usr/src/uts/sun4u/os/ |
| mach_mp_states.c | 32 * set_idle_cpu is called from idle() when a CPU becomes idle.
38 cpu_idle_ecache_scrub(CPU);
42 * unset_idle_cpu is called from idle() when a CPU is no longer idle.
48 cpu_busy_ecache_scrub(CPU);
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| cpc_subr.c | 56 * Called on the boot CPU during startup.
67 * Make sure the boot CPU gets set up.
69 kcpc_hw_startup_cpu(CPU->cpu_flags);
78 cpu_t *cp = CPU;
117 ASSERT(CPU->cpu_cpc_ctx != NULL);
119 atomic_or_uint(&CPU->cpu_cpc_ctx->kc_flags, KCPC_CTX_INVALID_STOPPED);
150 ASSERT(CPU->cpu_cpc_ctx != NULL);
152 pcbe_ops->pcbe_program(CPU->cpu_cpc_ctx);
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| mach_startup.c | 29 #include <sys/cpu.h>
83 * the CPU halt support. The cpu_halt_cpu() support is provided
84 * in the cpu module and it is referenced here with a pragma weak.
96 * The probe fires when the CPU undergoes an idle state change (e.g. halting)
97 * The agument passed is the state to which the CPU is transitioning.
109 intr_init(CPU); /* init interrupt request free list */
125 * the cpu id is present or not. We do this so that
145 * and each cpu id.
195 * Recompute the cpu frequency/delays based on tod as tod part
220 * Halt the present CPU until awoken via an interrupt
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| /onnv/onnv-gate/usr/src/uts/i86pc/os/ |
| mlsetup.c | 65 * to solve problems w/ creative cpu vendors
116 cpu[0]->cpu_self = cpu[0];
120 * Point at the hypervisor's virtual cpu structure
122 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
130 cpu[0]->cpu_pri_data = dummy_cpu_pri;
134 * when checking cpu features
179 * of the boot CPU. Note that if we choose to support CPUs that have
184 x86_feature = cpuid_pass1(cpu[0]);
212 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &
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| x_call.c | 33 #include <sys/cpu.h>
55 * on a target(s) CPU's work queue. Any synchronization is handled by passing
58 * Every CPU has xc_work_cnt, which indicates it has messages to process.
89 * of "->" happens in the slave cpu and "=>" happens in the master cpu as
126 * Decrement a CPU's work count
135 * Increment a CPU's work count and return the old value
161 cpu[msg->xc_master] == NULL || /* possible only during init */
162 queue == &cpu[msg->xc_master]->cpu_m.xc_free);
195 xc_init_cpu(struct cpu *cpup
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| /onnv/onnv-gate/usr/src/uts/common/sys/ |
| ftrace.h | 41 * both for the "ftrace_state" variable, and for the per-CPU variable
42 * "cpu[N]->cpu_ftrace_state".
73 * Default per-CPU event ring buffer size.
83 extern int ftrace_nent; /* Size of the per-CPU event ring buffer. */
103 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
108 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
113 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
118 if (CPU->cpu_ftrace.ftd_state & FTRACE_ENABLED) \
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| /onnv/onnv-gate/usr/src/uts/sun4v/os/ |
| cpc_subr.c | 56 * Called on the boot CPU during startup.
67 * Make sure the boot CPU gets set up.
69 kcpc_hw_startup_cpu(CPU->cpu_flags);
78 cpu_t *cp = CPU;
114 * Get next CPU module name from boot_cpu_compatible_list
136 ASSERT(CPU->cpu_cpc_ctx != NULL);
138 atomic_or_uint(&CPU->cpu_cpc_ctx->kc_flags, KCPC_CTX_INVALID_STOPPED);
169 ASSERT(CPU->cpu_cpc_ctx != NULL);
171 pcbe_ops->pcbe_program(CPU->cpu_cpc_ctx);
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| mach_startup.c | 32 #include <sys/cpu.h>
53 extern char htrap_tr0[]; /* prealloc buf for boot cpu */
59 * CPU IDLE optimization variables/routines
66 * The probe fires when the CPU undergoes an idle state change (e.g. hv yield)
67 * The agument passed is the state to which the CPU is transitioning.
86 mmu_fault_status_area + (MMFSA_SIZE * CPU->cpu_id);
88 intr_init(CPU); /* init interrupt request free list */
102 * Halt the present CPU until awoken via an interrupt
107 cpu_t *cpup = CPU;
115 * If this CPU is online then we should notate our haltin
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| /onnv/onnv-gate/usr/src/cmd/acct/ |
| prtacct.sh | 33 LOGIN CPU (MINS) KCORE-MINS CONNECT (MINS) DISK # OF # OF # DISK FEE
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| /onnv/onnv-gate/usr/src/uts/sun4u/serengeti/os/ |
| sg_unum.c | 51 * new cpu or board type.
91 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation) ||
92 IS_JAGUAR(cpunodes[CPU->cpu_id].implementation))
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| /onnv/onnv-gate/usr/src/uts/intel/ia32/os/ |
| cpc_subr.c | 27 * x86-specific routines used by the CPU Performance counter driver.
89 * If any CPU-bound contexts exist, we don't need to invalidate
96 * If this chip now has more than 1 active cpu, we must invalidate all
99 chip_pg = (pg_cmt_t *)pghw_find_pg(cpu[cpuid], PGHW_CHIP);
122 if (cpuid_getvendor(cpu[0]) == X86_VENDOR_Intel) {
187 return (kcpc_pcbe_tryload(cpuid_getvendorstr(CPU), cpuid_getfamily(CPU),
188 cpuid_getmodel(CPU), cpuid_getstep(CPU)));
194 ASSERT(CPU->cpu_cpc_ctx != NULL)
224 cpu_t *cpu, *p; local
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| /onnv/onnv-gate/usr/src/uts/sun4/ml/ |
| proc_init.s | 80 ! Initialize CPU state registers
82 ! The boot cpu and other cpus are different. The boot cpu has gone
108 ! cpu specific initialization.
123 ! It is very important to have a thread pointer and a cpu struct
130 ! we don't have the cache on yet for this CPU.
132 set cpu, %l3
133 sll %l1, CPTRSHIFT, %l2 ! offset into CPU vector.
134 ldn [%l3 + %l2], %l3 ! pointer to CPU struct
138 ! Set up any required cpu featur
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| /onnv/onnv-gate/usr/src/uts/sun4/os/ |
| mlsetup.c | 39 #include <sys/cpu.h>
167 THREAD_ONPROC(&t0, CPU);
194 CPU->cpu_thread = &t0;
195 CPU->cpu_dispthread = &t0;
197 CPU->cpu_disp = &cpu0_disp;
198 CPU->cpu_disp->disp_cpu = CPU;
199 CPU->cpu_idle_thread = &t0;
200 CPU->cpu_flags = CPU_RUNNING;
201 CPU->cpu_id = getprocessorid()
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| mp_states.c | 70 CPU->cpu_m.in_prom = 1;
76 kern_idle[CPU->cpu_id] = 1;
77 while (kern_idle[CPU->cpu_id])
80 CPU->cpu_m.in_prom = 0;
98 cpuid = CPU->cpu_id;
115 while (!cpu[i]->cpu_m.in_prom && ntries) {
121 * A cpu failing to idle is an error condition, since
124 if (!cpu[i]->cpu_m.in_prom) {
140 int cpuid = CPU->cpu_id;
162 while (cpu[i]->cpu_m.in_prom && ntries)
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| /onnv/onnv-gate/usr/src/uts/common/disp/ |
| disp_lock.c | 42 #include <sys/cpu.h>
45 * We check CPU_ON_INTR(CPU) when exiting a disp lock, rather than when
48 * we can safely load the CPU pointer without worrying about it changing.
79 if (CPU_ON_INTR(CPU) != 0)
94 if (CPU_ON_INTR(CPU) != 0)
97 if (CPU->cpu_kprunrun) {
108 if (CPU_ON_INTR(CPU) != 0)
122 if (CPU_ON_INTR(CPU) != 0)
165 if (CPU_ON_INTR(CPU) != 0)
|
| /onnv/onnv-gate/usr/src/uts/common/os/ |
| clock_tick.c | 34 #include <sys/cpu.h>
43 * with a tick to account for their use of CPU time.
93 * Array of online CPU pointers.
96 * Per-CPU, cache-aligned data structures to facilitate multi-threading.
108 * CPU online/offline.
111 * CPU id of the clock() CPU. Used to detect when the clock CPU
115 * CPU set of all online processors that can be X-called.
119 * for the task CPU time resource limit. We lower the number of call
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| unix_bb.c | 106 if (CPU_ON_INTR(CPU)) {
121 bb_last_who = CPU->cpu_id;
|
| pg.c | 62 * to a group of CPUs. Depending on the nature of the CPU relationship
80 * class specific callbacks to be invoked when the CPU related system
103 * Bootstrap CPU specific PG data
166 * CPU configuration callbacks
193 * CPU / cpupart configuration callbacks
238 pg_cmt_cpu_startup(CPU);
242 * Perform CPU 0 initialization
250 * Create the physical ID cache for the boot CPU
252 pghw_physid_create(CPU);
259 (void) pg_cpu_init(CPU, B_FALSE)
357 cpu_t *cpu; local
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| cpu_event.c | 28 * This file implements a CPU event notification mechanism to signal clients
29 * which are interested in CPU related events.
30 * Currently it only supports CPU idle state change events which will be
31 * triggered just before CPU entering hardware idle state and just after CPU
37 * 2) No protection for cpu_idle_cb_state because it's per-CPU data.
52 #include <sys/cpu.h>
67 /* Define normal state for CPU on different platforms. */
84 * To improve cache efficiency and avoid cache false sharing, CPU idle
89 * To access value of property m for CPU n, using following value as index
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| /onnv/onnv-gate/usr/src/cmd/picl/plugins/sun4u/schumacher/frutree/ |
| system-board.info | 33 NODE CPU location
34 PROP Label string r 0 "CPU 0"
36 PROP SlotType string r 0 "cpu"
39 NODE CPU location
40 PROP Label string r 0 "CPU 1"
42 PROP SlotType string r 0 "cpu"
72 * create the fru modules for CPU
74 name:/frutree/chassis/MB/SUNW,Netra-CP3010/CPU?GeoAddr=1
75 REFNODE cpu-module fru WITH _class:/PLATFORM_CLASS/cpu?ID=
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| /onnv/onnv-gate/usr/src/uts/sun4u/io/ |
| todstarfire.c | 132 if (cpu_sgnblkp[CPU->cpu_id] != NULL)
133 cpu_sgnblkp[CPU->cpu_id]->sigb_heartbeat++;
195 return (cpunodes[CPU->cpu_id].clock_freq);
|
| /onnv/onnv-gate/usr/src/cmd/pools/common/ |
| utils.h | 89 #define CPU "cpu"
93 #define CPU_SYSID "cpu.sys_id"
|
| /onnv/onnv-gate/usr/src/lib/fm/topo/libtopo/common/ |
| topo_hc.h | 49 #define CPU "cpu"
|
| /onnv/onnv-gate/usr/src/uts/i86pc/os/cpupm/ |
| cpupm_intel.c | 32 * Intel specific CPU power management support.
65 * it provides 4-bit OS input to the HW for the logical CPU, based on
96 family = cpuid_getfamily(CPU);
97 model = cpuid_getmodel(CPU);
|
| /onnv/onnv-gate/usr/src/uts/intel/dtrace/ |
| dtrace_isa.c | 49 uintptr_t caller = CPU->cpu_dtrace_caller;
51 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
52 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
120 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
142 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp;
192 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = sp;
306 (volatile uint16_t *)&cpu_core[CPU->cpu_id].cpuc_dtrace_flags;
511 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
512 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
659 cpu_core[CPU->cpu_id].cpuc_dtrace_illval = uaddr
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