1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * 29 * IEEE 1284 Parallel Port Device Driver 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/errno.h> 35 #include <sys/file.h> 36 #include <sys/cmn_err.h> 37 #include <sys/stropts.h> 38 #include <sys/debug.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/kmem.h> 42 #include <sys/ddi.h> 43 #include <sys/sunddi.h> 44 #include <sys/conf.h> /* req. by dev_ops flags MTSAFE etc. */ 45 #include <sys/modctl.h> /* for modldrv */ 46 #include <sys/stat.h> /* ddi_create_minor_node S_IFCHR */ 47 #include <sys/open.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/kstat.h> 50 51 #include <sys/prnio.h> 52 #include <sys/ecppreg.h> /* hw description */ 53 #include <sys/ecppio.h> /* ioctl description */ 54 #include <sys/ecppvar.h> /* driver description */ 55 #include <sys/dma_engine.h> 56 #include <sys/dma_i8237A.h> 57 58 /* 59 * Background 60 * ========== 61 * IEEE 1284-1994 standard defines "a signalling method for asynchronous, 62 * fully interlocked, bidirectional parallel communications between hosts 63 * and printers or other peripherals." (1.1) The standard defines 5 modes 64 * of operation - Compatibility, Nibble, Byte, ECP and EPP - which differ 65 * in direction, bandwidth, pins assignment, DMA capability, etc. 66 * 67 * Negotiation is a mechanism for moving between modes. Compatibility mode 68 * is a default mode, from which negotiations to other modes occur and 69 * to which both host and peripheral break in case of interface errors. 70 * Compatibility mode provides a unidirectional (forward) channel for 71 * communicating with old pre-1284 peripherals. 72 * 73 * Each mode has a number of phases. [Mode, phase] pair represents the 74 * interface state. Host initiates all transfers, though peripheral can 75 * request backchannel transfer by asserting nErr pin. 76 * 77 * Ecpp driver implements an IEEE 1284-compliant host using a combination 78 * of hardware and software. Hardware part is represented by a controller, 79 * which is a part of the SuperIO chip. Ecpp supports the following SuperIOs: 80 * PC82332/PC82336 (U5/U10/U60), PC97317 (U100), M1553 (Grover). 81 * Struct ecpp_hw describes each SuperIO and is determined in ecpp_attach(). 82 * 83 * Negotiation is performed in software. Transfer may be performed either 84 * in software by driving output pins for each byte (PIO method), or with 85 * hardware assistance - SuperIO has a 16-byte FIFO, which is filled by 86 * the driver (normally using DMA), while the chip performs the actual xfer. 87 * PIO is used for Nibble and Compat, DMA is used for ECP and Compat modes. 88 * 89 * Driver currently supports the following modes: 90 * 91 * - Compatibility mode: byte-wide forward channel ~50KB/sec; 92 * pp->io_mode defines PIO or DMA method of transfer; 93 * - Nibble mode: nibble-wide (4-bit) reverse channel ~30KB/sec; 94 * - ECP mode: byte-wide bidirectional channel (~1MB/sec); 95 * 96 * Theory of operation 97 * =================== 98 * The manner in which ecpp drives 1284 interface is that of a state machine. 99 * State is a combination of 1284 mode {ECPP_*_MODE}, 1284 phase {ECPP_PHASE_*} 100 * and transfer method {PIO, DMA}. State is a function of application actions 101 * {write(2), ioctl(2)} and peripheral reaction. 102 * 103 * 1284 interface state is described by the following variables: 104 * pp->current_mode -- 1284 mode used for forward transfers; 105 * pp->backchannel -- 1284 mode used for backward transfers; 106 * pp->curent_phase -- 1284 phase; 107 * 108 * Bidirectional operation in Compatibility mode is provided by a combination: 109 * pp->current_mode == ECPP_COMPAT_MODE && pp->backchannel == ECPP_NIBBLE_MODE 110 * ECPP_CENTRONICS means no backchannel 111 * 112 * Driver internal state is defined by pp->e_busy as follows: 113 * ECPP_IDLE -- idle, no active transfers; 114 * ECPP_BUSY -- transfer is in progress; 115 * ECPP_ERR -- have data to transfer, but peripheral can`t receive data; 116 * ECPP_FLUSH -- flushing the queues; 117 * 118 * When opened, driver is in ECPP_IDLE state, current mode is ECPP_CENTRONICS 119 * Default negotiation tries to negotiate to the best mode supported by printer, 120 * sets pp->current_mode and pp->backchannel accordingly. 121 * 122 * When output data arrives in M_DATA mblks ecpp_wput() puts them on the queue 123 * to let ecpp_wsrv() concatenate small blocks into one big transfer 124 * by copying them into pp->ioblock. If first the mblk data is bigger than 125 * pp->ioblock, then it is used instead of i/o block (pointed by pp->msg) 126 * 127 * Before starting the transfer the driver will check if peripheral is ready 128 * by calling ecpp_check_status() and if it is not, driver goes ECPP_ERR state 129 * and schedules ecpp_wsrv_timer() which would qenable() the wq, effectively 130 * rechecking the peripheral readiness and restarting itself until it is ready. 131 * The transfer is then started by calling ecpp_start(), driver goes ECPP_BUSY 132 * 133 * While transfer is in progress all arriving messages will be queued up. 134 * Transfer can end up in either of two ways: 135 * - interrupt occurs, ecpp_isr() checks if all the data was transferred, if so 136 * cleanup and go ECPP_IDLE, otherwise putback untransferred and qenable(); 137 * - ecpp_xfer_timeout() cancels the transfer and puts back untransferred data; 138 * 139 * PIO transfer method is very CPU intensive: for each sent byte the peripheral 140 * state is checked, then the byte is transfered and driver waits for an nAck 141 * interrupt; ecpp_isr() will then look if there is more data and if so 142 * triggers the soft interrupt, which transfers the next byte. PIO method 143 * is needed only for legacy printers which are sensitive to strobe problem 144 * (Bugid 4192788). 145 * 146 * ecpp_wsrv() is responsible for both starting transfers (ecpp_start()) and 147 * going idle (ecpp_idle_phase()). Many routines qenable() the write queue, 148 * meaning "check if there are pending requests, process them and go idle". 149 * 150 * In it`s idle state the driver will always try to listen to the backchannel 151 * (as advised by 1284). 152 * 153 * The mechanism for handling backchannel requests is as follows: 154 * - when the peripheral has data to send it asserts nErr pin 155 * (and also nAck in Nibble Mode) which results in an interrupt on the host; 156 * - ISR creates M_CTL message containing an ECPP_BACKCHANNEL byte and 157 * puts it back on the write queue; 158 * - ecpp_wsrv() gets M_CTL and calls ecpp_peripheral2host(), which kicks off 159 * the transfer; 160 * 161 * This way Nibble and ECP mode backchannel are implemented. 162 * If the read queue gets full, backchannel request is rejected. 163 * As the application reads data and queue size falls below the low watermark, 164 * ecpp_rsrv() gets called and enables the backchannel again. 165 * 166 * Future enhancements 167 * =================== 168 * 169 * Support new modes: Byte and EPP. 170 */ 171 172 #ifndef ECPP_DEBUG 173 #define ECPP_DEBUG 0 174 #endif /* ECPP_DEBUG */ 175 int ecpp_debug = ECPP_DEBUG; 176 177 int noecp = 0; /* flag not to use ECP mode */ 178 179 /* driver entry point fn definitions */ 180 static int ecpp_open(queue_t *, dev_t *, int, int, cred_t *); 181 static int ecpp_close(queue_t *, int, cred_t *); 182 static uint_t ecpp_isr(caddr_t); 183 static uint_t ecpp_softintr(caddr_t); 184 185 /* configuration entry point fn definitions */ 186 static int ecpp_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 187 static int ecpp_attach(dev_info_t *, ddi_attach_cmd_t); 188 static int ecpp_detach(dev_info_t *, ddi_detach_cmd_t); 189 static struct ecpp_hw_bind *ecpp_determine_sio_type(struct ecppunit *); 190 191 /* isr support routines */ 192 static uint_t ecpp_nErr_ihdlr(struct ecppunit *); 193 static uint_t ecpp_pio_ihdlr(struct ecppunit *); 194 static uint_t ecpp_dma_ihdlr(struct ecppunit *); 195 static uint_t ecpp_M1553_intr(struct ecppunit *); 196 197 /* configuration support routines */ 198 static void ecpp_get_props(struct ecppunit *); 199 200 /* Streams Routines */ 201 static int ecpp_wput(queue_t *, mblk_t *); 202 static int ecpp_wsrv(queue_t *); 203 static int ecpp_rsrv(queue_t *); 204 static void ecpp_flush(struct ecppunit *, int); 205 static void ecpp_start(struct ecppunit *, caddr_t, size_t); 206 207 /* ioctl handling */ 208 static void ecpp_putioc(queue_t *, mblk_t *); 209 static void ecpp_srvioc(queue_t *, mblk_t *); 210 static void ecpp_wput_iocdata_devid(queue_t *, mblk_t *, uintptr_t); 211 static void ecpp_putioc_copyout(queue_t *, mblk_t *, void *, int); 212 static void ecpp_putioc_stateful_copyin(queue_t *, mblk_t *, size_t); 213 static void ecpp_srvioc_devid(queue_t *, mblk_t *, 214 struct ecpp_device_id *, int *); 215 static void ecpp_srvioc_prnif(queue_t *, mblk_t *); 216 static void ecpp_ack_ioctl(queue_t *, mblk_t *); 217 static void ecpp_nack_ioctl(queue_t *, mblk_t *, int); 218 219 /* kstat routines */ 220 static void ecpp_kstat_init(struct ecppunit *); 221 static int ecpp_kstat_update(kstat_t *, int); 222 static int ecpp_kstatintr_update(kstat_t *, int); 223 224 /* dma routines */ 225 static void ecpp_putback_untransfered(struct ecppunit *, void *, uint_t); 226 static uint8_t ecpp_setup_dma_resources(struct ecppunit *, caddr_t, size_t); 227 static uint8_t ecpp_init_dma_xfer(struct ecppunit *, caddr_t, size_t); 228 229 /* pio routines */ 230 static void ecpp_pio_writeb(struct ecppunit *); 231 static void ecpp_xfer_cleanup(struct ecppunit *); 232 static uint8_t ecpp_prep_pio_xfer(struct ecppunit *, caddr_t, size_t); 233 234 /* misc */ 235 static uchar_t ecpp_reset_port_regs(struct ecppunit *); 236 static void ecpp_xfer_timeout(void *); 237 static void ecpp_fifo_timer(void *); 238 static void ecpp_wsrv_timer(void *); 239 static uchar_t dcr_write(struct ecppunit *, uint8_t); 240 static uchar_t ecr_write(struct ecppunit *, uint8_t); 241 static uchar_t ecpp_check_status(struct ecppunit *); 242 static int ecpp_backchan_req(struct ecppunit *); 243 static void ecpp_untimeout_unblock(struct ecppunit *, timeout_id_t *); 244 static uint_t ecpp_get_prn_ifcap(struct ecppunit *); 245 246 /* stubs */ 247 static void empty_config_mode(struct ecppunit *); 248 static void empty_mask_intr(struct ecppunit *); 249 250 /* PC87332 support */ 251 static int pc87332_map_regs(struct ecppunit *); 252 static void pc87332_unmap_regs(struct ecppunit *); 253 static int pc87332_config_chip(struct ecppunit *); 254 static void pc87332_config_mode(struct ecppunit *); 255 static uint8_t pc87332_read_config_reg(struct ecppunit *, uint8_t); 256 static void pc87332_write_config_reg(struct ecppunit *, uint8_t, uint8_t); 257 static void cheerio_mask_intr(struct ecppunit *); 258 static void cheerio_unmask_intr(struct ecppunit *); 259 static int cheerio_dma_start(struct ecppunit *); 260 static int cheerio_dma_stop(struct ecppunit *, size_t *); 261 static size_t cheerio_getcnt(struct ecppunit *); 262 static void cheerio_reset_dcsr(struct ecppunit *); 263 264 /* PC97317 support */ 265 static int pc97317_map_regs(struct ecppunit *); 266 static void pc97317_unmap_regs(struct ecppunit *); 267 static int pc97317_config_chip(struct ecppunit *); 268 static void pc97317_config_mode(struct ecppunit *); 269 270 /* M1553 Southbridge support */ 271 static int m1553_map_regs(struct ecppunit *pp); 272 static void m1553_unmap_regs(struct ecppunit *pp); 273 static int m1553_config_chip(struct ecppunit *); 274 static uint8_t m1553_read_config_reg(struct ecppunit *, uint8_t); 275 static void m1553_write_config_reg(struct ecppunit *, uint8_t, uint8_t); 276 277 /* M1553 Southbridge DMAC 8237 support routines */ 278 static int dma8237_dma_start(struct ecppunit *); 279 static int dma8237_dma_stop(struct ecppunit *, size_t *); 280 static size_t dma8237_getcnt(struct ecppunit *); 281 static void dma8237_write_addr(struct ecppunit *, uint32_t); 282 static void dma8237_write_count(struct ecppunit *, uint32_t); 283 static uint32_t dma8237_read_count(struct ecppunit *); 284 static void dma8237_write(struct ecppunit *, int, uint8_t); 285 static uint8_t dma8237_read(struct ecppunit *, int); 286 #ifdef INCLUDE_DMA8237_READ_ADDR 287 static uint32_t dma8237_read_addr(struct ecppunit *); 288 #endif 289 290 /* i86 PC support rountines */ 291 292 #if defined(__x86) 293 static int x86_dma_start(struct ecppunit *); 294 static int x86_dma_stop(struct ecppunit *, size_t *); 295 static int x86_map_regs(struct ecppunit *); 296 static void x86_unmap_regs(struct ecppunit *); 297 static int x86_config_chip(struct ecppunit *); 298 static size_t x86_getcnt(struct ecppunit *); 299 #endif 300 301 /* IEEE 1284 phase transitions */ 302 static void ecpp_1284_init_interface(struct ecppunit *); 303 static int ecpp_1284_termination(struct ecppunit *); 304 static uchar_t ecpp_idle_phase(struct ecppunit *); 305 static int ecp_forward2reverse(struct ecppunit *); 306 static int ecp_reverse2forward(struct ecppunit *); 307 static int read_nibble_backchan(struct ecppunit *); 308 309 /* reverse transfers */ 310 static uint_t ecpp_peripheral2host(struct ecppunit *); 311 static uchar_t ecp_peripheral2host(struct ecppunit *); 312 static uchar_t nibble_peripheral2host(struct ecppunit *pp, uint8_t *); 313 static int ecpp_getdevid(struct ecppunit *, uint8_t *, int *, int); 314 static void ecpp_ecp_read_timeout(void *); 315 static void ecpp_ecp_read_completion(struct ecppunit *); 316 317 /* IEEE 1284 mode transitions */ 318 static void ecpp_default_negotiation(struct ecppunit *); 319 static int ecpp_mode_negotiation(struct ecppunit *, uchar_t); 320 static int ecpp_1284_negotiation(struct ecppunit *, uint8_t, uint8_t *); 321 static int ecp_negotiation(struct ecppunit *); 322 static int nibble_negotiation(struct ecppunit *); 323 static int devidnib_negotiation(struct ecppunit *); 324 325 /* IEEE 1284 utility routines */ 326 static int wait_dsr(struct ecppunit *, uint8_t, uint8_t, int); 327 328 /* debugging functions */ 329 static void ecpp_error(dev_info_t *, char *, ...); 330 static uchar_t ecpp_get_error_status(uchar_t); 331 332 /* 333 * Chip-dependent structures 334 */ 335 static ddi_dma_attr_t cheerio_dma_attr = { 336 DMA_ATTR_VERSION, /* version */ 337 0x00000000ull, /* dlim_addr_lo */ 338 0xfffffffeull, /* dlim_addr_hi */ 339 0xffffff, /* DMA counter register */ 340 1, /* DMA address alignment */ 341 0x74, /* burst sizes */ 342 0x0001, /* min effective DMA size */ 343 0xffff, /* maximum transfer size */ 344 0xffff, /* segment boundary */ 345 1, /* s/g list length */ 346 1, /* granularity of device */ 347 0 /* DMA flags */ 348 }; 349 350 static struct ecpp_hw pc87332 = { 351 pc87332_map_regs, 352 pc87332_unmap_regs, 353 pc87332_config_chip, 354 pc87332_config_mode, 355 cheerio_mask_intr, 356 cheerio_unmask_intr, 357 cheerio_dma_start, 358 cheerio_dma_stop, 359 cheerio_getcnt, 360 &cheerio_dma_attr 361 }; 362 363 static struct ecpp_hw pc97317 = { 364 pc97317_map_regs, 365 pc97317_unmap_regs, 366 pc97317_config_chip, 367 pc97317_config_mode, 368 cheerio_mask_intr, 369 cheerio_unmask_intr, 370 cheerio_dma_start, 371 cheerio_dma_stop, 372 cheerio_getcnt, 373 &cheerio_dma_attr 374 }; 375 376 static ddi_dma_attr_t i8237_dma_attr = { 377 DMA_ATTR_VERSION, /* version */ 378 0x00000000ull, /* dlim_addr_lo */ 379 0xfffffffeull, /* dlim_addr_hi */ 380 0xffff, /* DMA counter register */ 381 1, /* DMA address alignment */ 382 0x01, /* burst sizes */ 383 0x0001, /* min effective DMA size */ 384 0xffff, /* maximum transfer size */ 385 0x7fff, /* segment boundary */ 386 1, /* s/g list length */ 387 1, /* granularity of device */ 388 0 /* DMA flags */ 389 }; 390 391 static struct ecpp_hw m1553 = { 392 m1553_map_regs, 393 m1553_unmap_regs, 394 m1553_config_chip, 395 empty_config_mode, /* no config_mode */ 396 empty_mask_intr, /* no mask_intr */ 397 empty_mask_intr, /* no unmask_intr */ 398 dma8237_dma_start, 399 dma8237_dma_stop, 400 dma8237_getcnt, 401 &i8237_dma_attr 402 }; 403 404 #if defined(__x86) 405 static ddi_dma_attr_t sb_dma_attr = { 406 DMA_ATTR_VERSION, /* version */ 407 0x00000000ull, /* dlim_addr_lo */ 408 0xffffff, /* dlim_addr_hi */ 409 0xffff, /* DMA counter register */ 410 1, /* DMA address alignment */ 411 0x01, /* burst sizes */ 412 0x0001, /* min effective DMA size */ 413 0xffffffff, /* maximum transfer size */ 414 0xffff, /* segment boundary */ 415 1, /* s/g list length */ 416 1, /* granularity of device */ 417 0 /* DMA flags */ 418 }; 419 420 static struct ecpp_hw x86 = { 421 x86_map_regs, 422 x86_unmap_regs, 423 x86_config_chip, 424 empty_config_mode, /* no config_mode */ 425 empty_mask_intr, /* no mask_intr */ 426 empty_mask_intr, /* no unmask_intr */ 427 x86_dma_start, 428 x86_dma_stop, 429 x86_getcnt, 430 &sb_dma_attr 431 }; 432 #endif 433 434 /* 435 * list of supported devices 436 */ 437 struct ecpp_hw_bind ecpp_hw_bind[] = { 438 { "ns87317-ecpp", &pc97317, "PC97317" }, 439 { "pnpALI,1533,3", &m1553, "M1553" }, 440 { "ecpp", &pc87332, "PC87332" }, 441 #if defined(__x86) 442 { "lp", &x86, "i86pc"}, 443 #endif 444 }; 445 446 static ddi_device_acc_attr_t acc_attr = { 447 DDI_DEVICE_ATTR_V0, 448 DDI_STRUCTURE_LE_ACC, 449 DDI_STRICTORDER_ACC 450 }; 451 452 static struct ecpp_transfer_parms default_xfer_parms = { 453 FWD_TIMEOUT_DEFAULT, /* write timeout in seconds */ 454 ECPP_CENTRONICS /* supported mode */ 455 }; 456 457 /* prnio interface info string */ 458 static const char prn_ifinfo[] = PRN_PARALLEL; 459 460 /* prnio timeouts */ 461 static const struct prn_timeouts prn_timeouts_default = { 462 FWD_TIMEOUT_DEFAULT, /* forward timeout */ 463 REV_TIMEOUT_DEFAULT /* reverse timeout */ 464 }; 465 466 static int ecpp_isr_max_delay = ECPP_ISR_MAX_DELAY; 467 static int ecpp_def_timeout = 90; /* left in for 2.7 compatibility */ 468 469 static void *ecppsoft_statep; 470 471 /* 472 * STREAMS framework manages locks for these structures 473 */ 474 _NOTE(SCHEME_PROTECTS_DATA("unique per call", iocblk)) 475 _NOTE(SCHEME_PROTECTS_DATA("unique per call", datab)) 476 _NOTE(SCHEME_PROTECTS_DATA("unique per call", msgb)) 477 _NOTE(SCHEME_PROTECTS_DATA("unique per call", queue)) 478 _NOTE(SCHEME_PROTECTS_DATA("unique per call", copyreq)) 479 _NOTE(SCHEME_PROTECTS_DATA("unique per call", stroptions)) 480 481 struct module_info ecppinfo = { 482 /* id, name, min pkt siz, max pkt siz, hi water, low water */ 483 42, "ecpp", 0, IO_BLOCK_SZ, ECPPHIWAT, ECPPLOWAT 484 }; 485 486 static struct qinit ecpp_rinit = { 487 putq, ecpp_rsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL 488 }; 489 490 static struct qinit ecpp_wint = { 491 ecpp_wput, ecpp_wsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL 492 }; 493 494 struct streamtab ecpp_str_info = { 495 &ecpp_rinit, &ecpp_wint, NULL, NULL 496 }; 497 498 static struct cb_ops ecpp_cb_ops = { 499 nodev, /* cb_open */ 500 nodev, /* cb_close */ 501 nodev, /* cb_strategy */ 502 nodev, /* cb_print */ 503 nodev, /* cb_dump */ 504 nodev, /* cb_read */ 505 nodev, /* cb_write */ 506 nodev, /* cb_ioctl */ 507 nodev, /* cb_devmap */ 508 nodev, /* cb_mmap */ 509 nodev, /* cb_segmap */ 510 nochpoll, /* cb_chpoll */ 511 ddi_prop_op, /* cb_prop_op */ 512 &ecpp_str_info, /* cb_stream */ 513 (D_NEW | D_MP | D_MTPERQ) /* cb_flag */ 514 }; 515 516 /* 517 * Declare ops vectors for auto configuration. 518 */ 519 struct dev_ops ecpp_ops = { 520 DEVO_REV, /* devo_rev */ 521 0, /* devo_refcnt */ 522 ecpp_getinfo, /* devo_getinfo */ 523 nulldev, /* devo_identify */ 524 nulldev, /* devo_probe */ 525 ecpp_attach, /* devo_attach */ 526 ecpp_detach, /* devo_detach */ 527 nodev, /* devo_reset */ 528 &ecpp_cb_ops, /* devo_cb_ops */ 529 (struct bus_ops *)NULL, /* devo_bus_ops */ 530 nulldev, /* devo_power */ 531 ddi_quiesce_not_needed, /* devo_quiesce */ 532 }; 533 534 extern struct mod_ops mod_driverops; 535 536 static struct modldrv ecppmodldrv = { 537 &mod_driverops, /* type of module - driver */ 538 "parallel port driver", 539 &ecpp_ops, 540 }; 541 542 static struct modlinkage ecppmodlinkage = { 543 MODREV_1, 544 &ecppmodldrv, 545 0 546 }; 547 548 549 /* 550 * 551 * DDI/DKI entry points and supplementary routines 552 * 553 */ 554 555 556 int 557 _init(void) 558 { 559 int error; 560 561 if ((error = mod_install(&ecppmodlinkage)) == 0) { 562 (void) ddi_soft_state_init(&ecppsoft_statep, 563 sizeof (struct ecppunit), 1); 564 } 565 566 return (error); 567 } 568 569 int 570 _fini(void) 571 { 572 int error; 573 574 if ((error = mod_remove(&ecppmodlinkage)) == 0) { 575 ddi_soft_state_fini(&ecppsoft_statep); 576 } 577 578 return (error); 579 } 580 581 int 582 _info(struct modinfo *modinfop) 583 { 584 return (mod_info(&ecppmodlinkage, modinfop)); 585 } 586 587 static int 588 ecpp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 589 { 590 int instance; 591 char name[16]; 592 struct ecppunit *pp; 593 struct ecpp_hw_bind *hw_bind; 594 595 instance = ddi_get_instance(dip); 596 597 switch (cmd) { 598 case DDI_ATTACH: 599 break; 600 601 case DDI_RESUME: 602 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) { 603 return (DDI_FAILURE); 604 } 605 606 mutex_enter(&pp->umutex); 607 608 pp->suspended = FALSE; 609 610 /* 611 * Initialize the chip and restore current mode if needed 612 */ 613 (void) ECPP_CONFIG_CHIP(pp); 614 (void) ecpp_reset_port_regs(pp); 615 616 if (pp->oflag == TRUE) { 617 int current_mode = pp->current_mode; 618 619 (void) ecpp_1284_termination(pp); 620 (void) ecpp_mode_negotiation(pp, current_mode); 621 } 622 623 mutex_exit(&pp->umutex); 624 625 return (DDI_SUCCESS); 626 627 default: 628 return (DDI_FAILURE); 629 } 630 631 if (ddi_soft_state_zalloc(ecppsoft_statep, instance) != 0) { 632 ecpp_error(dip, "ddi_soft_state_zalloc failed\n"); 633 goto fail; 634 } 635 636 pp = ddi_get_soft_state(ecppsoft_statep, instance); 637 638 pp->dip = dip; 639 pp->suspended = FALSE; 640 641 /* 642 * Determine SuperIO type and set chip-dependent variables 643 */ 644 hw_bind = ecpp_determine_sio_type(pp); 645 646 if (hw_bind == NULL) { 647 cmn_err(CE_NOTE, "parallel port controller not supported"); 648 goto fail_sio; 649 } else { 650 pp->hw = hw_bind->hw; 651 ecpp_error(pp->dip, "SuperIO type: %s\n", hw_bind->info); 652 } 653 654 /* 655 * Map registers 656 */ 657 if (ECPP_MAP_REGS(pp) != SUCCESS) { 658 goto fail_map; 659 } 660 661 if (ddi_dma_alloc_handle(dip, pp->hw->attr, DDI_DMA_DONTWAIT, 662 NULL, &pp->dma_handle) != DDI_SUCCESS) { 663 ecpp_error(dip, "ecpp_attach: failed ddi_dma_alloc_handle\n"); 664 goto fail_dma; 665 } 666 667 if (ddi_get_iblock_cookie(dip, 0, 668 &pp->ecpp_trap_cookie) != DDI_SUCCESS) { 669 ecpp_error(dip, "ecpp_attach: failed ddi_get_iblock_cookie\n"); 670 goto fail_ibc; 671 } 672 673 mutex_init(&pp->umutex, NULL, MUTEX_DRIVER, 674 (void *)pp->ecpp_trap_cookie); 675 676 cv_init(&pp->pport_cv, NULL, CV_DRIVER, NULL); 677 678 if (ddi_add_intr(dip, 0, &pp->ecpp_trap_cookie, NULL, ecpp_isr, 679 (caddr_t)pp) != DDI_SUCCESS) { 680 ecpp_error(dip, "ecpp_attach: failed to add hard intr\n"); 681 goto fail_intr; 682 } 683 684 if (ddi_add_softintr(dip, DDI_SOFTINT_LOW, 685 &pp->softintr_id, 0, 0, ecpp_softintr, 686 (caddr_t)pp) != DDI_SUCCESS) { 687 ecpp_error(dip, "ecpp_attach: failed to add soft intr\n"); 688 goto fail_softintr; 689 } 690 691 (void) sprintf(name, "ecpp%d", instance); 692 693 if (ddi_create_minor_node(dip, name, S_IFCHR, instance, 694 DDI_NT_PRINTER, NULL) == DDI_FAILURE) { 695 ecpp_error(dip, "ecpp_attach: create_minor_node failed\n"); 696 goto fail_minor; 697 } 698 699 pp->ioblock = (caddr_t)kmem_alloc(IO_BLOCK_SZ, KM_SLEEP); 700 if (pp->ioblock == NULL) { 701 ecpp_error(dip, "ecpp_attach: kmem_alloc failed\n"); 702 goto fail_iob; 703 } else { 704 ecpp_error(pp->dip, "ecpp_attach: ioblock=0x%x\n", pp->ioblock); 705 } 706 707 ecpp_get_props(pp); 708 #if defined(__x86) 709 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) { 710 if (ddi_dmae_alloc(dip, pp->uh.x86.chn, 711 DDI_DMA_DONTWAIT, NULL) == DDI_SUCCESS) 712 ecpp_error(pp->dip, "dmae_alloc success!\n"); 713 } 714 #endif 715 if (ECPP_CONFIG_CHIP(pp) == FAILURE) { 716 ecpp_error(pp->dip, "config_chip failed.\n"); 717 goto fail_config; 718 } 719 720 ecpp_kstat_init(pp); 721 722 ddi_report_dev(dip); 723 724 return (DDI_SUCCESS); 725 726 fail_config: 727 ddi_prop_remove_all(dip); 728 kmem_free(pp->ioblock, IO_BLOCK_SZ); 729 fail_iob: 730 ddi_remove_minor_node(dip, NULL); 731 fail_minor: 732 ddi_remove_softintr(pp->softintr_id); 733 fail_softintr: 734 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie); 735 fail_intr: 736 mutex_destroy(&pp->umutex); 737 cv_destroy(&pp->pport_cv); 738 fail_ibc: 739 ddi_dma_free_handle(&pp->dma_handle); 740 fail_dma: 741 ECPP_UNMAP_REGS(pp); 742 fail_map: 743 fail_sio: 744 ddi_soft_state_free(ecppsoft_statep, instance); 745 fail: 746 ecpp_error(dip, "ecpp_attach: failed.\n"); 747 748 return (DDI_FAILURE); 749 } 750 751 static int 752 ecpp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 753 { 754 int instance; 755 struct ecppunit *pp; 756 757 instance = ddi_get_instance(dip); 758 759 switch (cmd) { 760 case DDI_DETACH: 761 break; 762 763 case DDI_SUSPEND: 764 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) { 765 return (DDI_FAILURE); 766 } 767 768 mutex_enter(&pp->umutex); 769 ASSERT(pp->suspended == FALSE); 770 771 pp->suspended = TRUE; /* prevent new transfers */ 772 773 /* 774 * Wait if there's any activity on the port 775 */ 776 if ((pp->e_busy == ECPP_BUSY) || (pp->e_busy == ECPP_FLUSH)) { 777 (void) cv_timedwait(&pp->pport_cv, &pp->umutex, 778 ddi_get_lbolt() + 779 SUSPEND_TOUT * drv_usectohz(1000000)); 780 if ((pp->e_busy == ECPP_BUSY) || 781 (pp->e_busy == ECPP_FLUSH)) { 782 pp->suspended = FALSE; 783 mutex_exit(&pp->umutex); 784 ecpp_error(pp->dip, 785 "ecpp_detach: suspend timeout\n"); 786 return (DDI_FAILURE); 787 } 788 } 789 790 mutex_exit(&pp->umutex); 791 return (DDI_SUCCESS); 792 793 default: 794 return (DDI_FAILURE); 795 } 796 797 pp = ddi_get_soft_state(ecppsoft_statep, instance); 798 #if defined(__x86) 799 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) 800 (void) ddi_dmae_release(pp->dip, pp->uh.x86.chn); 801 #endif 802 if (pp->dma_handle != NULL) 803 ddi_dma_free_handle(&pp->dma_handle); 804 805 ddi_remove_minor_node(dip, NULL); 806 807 ddi_remove_softintr(pp->softintr_id); 808 809 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie); 810 811 if (pp->ksp) { 812 kstat_delete(pp->ksp); 813 } 814 if (pp->intrstats) { 815 kstat_delete(pp->intrstats); 816 } 817 818 cv_destroy(&pp->pport_cv); 819 820 mutex_destroy(&pp->umutex); 821 822 ECPP_UNMAP_REGS(pp); 823 824 kmem_free(pp->ioblock, IO_BLOCK_SZ); 825 826 ddi_prop_remove_all(dip); 827 828 ddi_soft_state_free(ecppsoft_statep, instance); 829 830 return (DDI_SUCCESS); 831 832 } 833 834 /* 835 * ecpp_get_props() reads ecpp.conf for user defineable tuneables. 836 * If the file or a particular variable is not there, a default value 837 * is assigned. 838 */ 839 840 static void 841 ecpp_get_props(struct ecppunit *pp) 842 { 843 char *prop; 844 #if defined(__x86) 845 int len; 846 int value; 847 #endif 848 /* 849 * If fast_centronics is TRUE, non-compliant IEEE 1284 850 * peripherals ( Centronics peripherals) will operate in DMA mode. 851 * Transfers betwee main memory and the device will be via DMA; 852 * peripheral handshaking will be conducted by superio logic. 853 * If ecpp can not read the variable correctly fast_centronics will 854 * be set to FALSE. In this case, transfers and handshaking 855 * will be conducted by PIO for Centronics devices. 856 */ 857 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0, 858 "fast-centronics", &prop) == DDI_PROP_SUCCESS) { 859 pp->fast_centronics = 860 (strcmp(prop, "true") == 0) ? TRUE : FALSE; 861 ddi_prop_free(prop); 862 } else { 863 pp->fast_centronics = FALSE; 864 } 865 866 /* 867 * If fast-1284-compatible is set to TRUE, when ecpp communicates 868 * with IEEE 1284 compliant peripherals, data transfers between 869 * main memory and the parallel port will be conducted by DMA. 870 * Handshaking between the port and peripheral will be conducted 871 * by superio logic. This is the default characteristic. If 872 * fast-1284-compatible is set to FALSE, transfers and handshaking 873 * will be conducted by PIO. 874 */ 875 876 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0, 877 "fast-1284-compatible", &prop) == DDI_PROP_SUCCESS) { 878 pp->fast_compat = (strcmp(prop, "true") == 0) ? TRUE : FALSE; 879 ddi_prop_free(prop); 880 } else { 881 pp->fast_compat = TRUE; 882 } 883 884 /* 885 * Some centronics peripherals require the nInit signal to be 886 * toggled to reset the device. If centronics_init_seq is set 887 * to TRUE, ecpp will toggle the nInit signal upon every ecpp_open(). 888 * Applications have the opportunity to toggle the nInit signal 889 * with ioctl(2) calls as well. The default is to set it to FALSE. 890 */ 891 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0, 892 "centronics-init-seq", &prop) == DDI_PROP_SUCCESS) { 893 pp->init_seq = (strcmp(prop, "true") == 0) ? TRUE : FALSE; 894 ddi_prop_free(prop); 895 } else { 896 pp->init_seq = FALSE; 897 } 898 899 /* 900 * If one of the centronics status signals are in an erroneous 901 * state, ecpp_wsrv() will be reinvoked centronics-retry ms to 902 * check if the status is ok to transfer. If the property is not 903 * found, wsrv_retry will be set to CENTRONICS_RETRY ms. 904 */ 905 pp->wsrv_retry = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 906 "centronics-retry", CENTRONICS_RETRY); 907 908 /* 909 * In PIO mode, ecpp_isr() will loop for wait for the busy signal 910 * to be deasserted before transferring the next byte. wait_for_busy 911 * is specificied in microseconds. If the property is not found 912 * ecpp_isr() will wait for a maximum of WAIT_FOR_BUSY us. 913 */ 914 pp->wait_for_busy = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 915 "centronics-wait-for-busy", WAIT_FOR_BUSY); 916 917 /* 918 * In PIO mode, centronics transfers must hold the data signals 919 * for a data_setup_time milliseconds before the strobe is asserted. 920 */ 921 pp->data_setup_time = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 922 "centronics-data-setup-time", DATA_SETUP_TIME); 923 924 /* 925 * In PIO mode, centronics transfers asserts the strobe signal 926 * for a period of strobe_pulse_width milliseconds. 927 */ 928 pp->strobe_pulse_width = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 929 "centronics-strobe-pulse-width", STROBE_PULSE_WIDTH); 930 931 /* 932 * Upon a transfer the peripheral, ecpp waits write_timeout seconds 933 * for the transmission to complete. 934 */ 935 default_xfer_parms.write_timeout = ddi_prop_get_int(DDI_DEV_T_ANY, 936 pp->dip, 0, "ecpp-transfer-timeout", ecpp_def_timeout); 937 938 pp->xfer_parms = default_xfer_parms; 939 940 /* 941 * Get dma channel for M1553 942 */ 943 if (pp->hw == &m1553) { 944 pp->uh.m1553.chn = ddi_prop_get_int(DDI_DEV_T_ANY, 945 pp->dip, 0, "dma-channel", 0x1); 946 ecpp_error(pp->dip, "ecpp_get_prop:chn=%x\n", pp->uh.m1553.chn); 947 } 948 #if defined(__x86) 949 len = sizeof (value); 950 /* Get dma channel for i86 pc */ 951 if (pp->hw == &x86) { 952 if (ddi_prop_op(DDI_DEV_T_ANY, pp->dip, PROP_LEN_AND_VAL_BUF, 953 DDI_PROP_DONTPASS, "dma-channels", (caddr_t)&value, &len) 954 != DDI_PROP_SUCCESS) { 955 ecpp_error(pp->dip, "No dma channel found\n"); 956 pp->uh.x86.chn = 0xff; 957 pp->fast_compat = FALSE; 958 pp->noecpregs = TRUE; 959 } else 960 pp->uh.x86.chn = (uint8_t)value; 961 } 962 #endif 963 /* 964 * these properties are not yet public 965 */ 966 pp->ecp_rev_speed = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 967 "ecp-rev-speed", ECP_REV_SPEED); 968 969 pp->rev_watchdog = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 970 "rev-watchdog", REV_WATCHDOG); 971 972 ecpp_error(pp->dip, 973 "ecpp_get_prop: fast_centronics=%x, fast-1284=%x\n" 974 "ecpp_get_prop: wsrv_retry=%d, wait_for_busy=%d\n" 975 "ecpp_get_prop: data_setup=%d, strobe_pulse=%d\n" 976 "ecpp_get_prop: transfer-timeout=%d\n", 977 pp->fast_centronics, pp->fast_compat, 978 pp->wsrv_retry, pp->wait_for_busy, 979 pp->data_setup_time, pp->strobe_pulse_width, 980 pp->xfer_parms.write_timeout); 981 } 982 983 /*ARGSUSED*/ 984 int 985 ecpp_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 986 { 987 dev_t dev = (dev_t)arg; 988 struct ecppunit *pp; 989 int instance, ret; 990 991 instance = getminor(dev); 992 993 switch (infocmd) { 994 case DDI_INFO_DEVT2DEVINFO: 995 pp = ddi_get_soft_state(ecppsoft_statep, instance); 996 if (pp != NULL) { 997 *result = pp->dip; 998 ret = DDI_SUCCESS; 999 } else { 1000 ret = DDI_FAILURE; 1001 } 1002 break; 1003 1004 case DDI_INFO_DEVT2INSTANCE: 1005 *result = (void *)(uintptr_t)instance; 1006 ret = DDI_SUCCESS; 1007 break; 1008 1009 default: 1010 ret = DDI_FAILURE; 1011 break; 1012 } 1013 1014 return (ret); 1015 } 1016 1017 /*ARGSUSED2*/ 1018 static int 1019 ecpp_open(queue_t *q, dev_t *dev, int flag, int sflag, cred_t *credp) 1020 { 1021 struct ecppunit *pp; 1022 int instance; 1023 struct stroptions *sop; 1024 mblk_t *mop; 1025 1026 instance = getminor(*dev); 1027 1028 if (instance < 0) { 1029 return (ENXIO); 1030 } 1031 1032 pp = (struct ecppunit *)ddi_get_soft_state(ecppsoft_statep, instance); 1033 1034 if (pp == NULL) { 1035 return (ENXIO); 1036 } 1037 1038 mutex_enter(&pp->umutex); 1039 1040 /* 1041 * Parallel port is an exclusive-use device 1042 * thus providing print job integrity 1043 */ 1044 if (pp->oflag == TRUE) { 1045 ecpp_error(pp->dip, "ecpp open failed"); 1046 mutex_exit(&pp->umutex); 1047 return (EBUSY); 1048 } 1049 1050 pp->oflag = TRUE; 1051 1052 /* initialize state variables */ 1053 pp->prn_timeouts = prn_timeouts_default; 1054 pp->xfer_parms = default_xfer_parms; 1055 pp->current_mode = ECPP_CENTRONICS; 1056 pp->backchannel = ECPP_CENTRONICS; 1057 pp->current_phase = ECPP_PHASE_PO; 1058 pp->port = ECPP_PORT_DMA; 1059 pp->instance = instance; 1060 pp->timeout_error = 0; 1061 pp->saved_dsr = DSR_READ(pp); 1062 pp->ecpp_drain_counter = 0; 1063 pp->