1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 /* IntelVersion: 1.218 scm_100309_002210 */ 29 30 #include "ixgbe_common.h" 31 #include "ixgbe_api.h" 32 33 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 34 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 35 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 36 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 37 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 38 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 39 u16 count); 40 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 41 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 42 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 43 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 44 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); 45 46 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 47 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 48 u16 *san_mac_offset); 49 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan); 50 51 /* 52 * ixgbe_init_ops_generic - Inits function ptrs 53 * @hw: pointer to the hardware structure 54 * 55 * Initialize the function pointers. 56 */ 57 s32 58 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 61 struct ixgbe_mac_info *mac = &hw->mac; 62 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 63 64 DEBUGFUNC("ixgbe_init_ops_generic"); 65 66 /* EEPROM */ 67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 68 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 69 if (eec & (1 << 8)) 70 eeprom->ops.read = &ixgbe_read_eerd_generic; 71 else 72 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 73 eeprom->ops.write = &ixgbe_write_eeprom_generic; 74 eeprom->ops.validate_checksum = 75 &ixgbe_validate_eeprom_checksum_generic; 76 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 77 78 /* MAC */ 79 mac->ops.init_hw = &ixgbe_init_hw_generic; 80 mac->ops.reset_hw = NULL; 81 mac->ops.start_hw = &ixgbe_start_hw_generic; 82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 83 mac->ops.get_media_type = NULL; 84 mac->ops.get_supported_physical_layer = NULL; 85 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 86 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 87 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 88 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 89 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 90 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 91 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 92 93 /* LEDs */ 94 mac->ops.led_on = &ixgbe_led_on_generic; 95 mac->ops.led_off = &ixgbe_led_off_generic; 96 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 97 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 98 99 /* RAR, Multicast, VLAN */ 100 mac->ops.set_rar = &ixgbe_set_rar_generic; 101 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 102 mac->ops.insert_mac_addr = NULL; 103 mac->ops.set_vmdq = NULL; 104 mac->ops.clear_vmdq = NULL; 105 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 106 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 107 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 108 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 109 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 110 mac->ops.clear_vfta = NULL; 111 mac->ops.set_vfta = NULL; 112 mac->ops.init_uta_tables = NULL; 113 114 /* Flow Control */ 115 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 116 117 /* Link */ 118 mac->ops.get_link_capabilities = NULL; 119 mac->ops.setup_link = NULL; 120 mac->ops.check_link = NULL; 121 122 return (IXGBE_SUCCESS); 123 } 124 125 /* 126 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 127 * @hw: pointer to hardware structure 128 * 129 * Starts the hardware by filling the bus info structure and media type, clears 130 * all on chip counters, initializes receive address registers, multicast 131 * table, VLAN filter table, calls routine to set up link and flow control 132 * settings, and leaves transmit and receive units disabled and uninitialized 133 */ 134 s32 135 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 136 { 137 u32 ctrl_ext; 138 139 DEBUGFUNC("ixgbe_start_hw_generic"); 140 141 /* Set the media type */ 142 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 143 144 /* PHY ops initialization must be done in reset_hw() */ 145 146 /* Clear the VLAN filter table */ 147 hw->mac.ops.clear_vfta(hw); 148 149 /* Clear statistics registers */ 150 hw->mac.ops.clear_hw_cntrs(hw); 151 152 /* Set No Snoop Disable */ 153 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 154 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 155 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 156 IXGBE_WRITE_FLUSH(hw); 157 158 /* Setup flow control */ 159 (void) ixgbe_setup_fc(hw, 0); 160 161 /* Clear adapter stopped flag */ 162 hw->adapter_stopped = false; 163 164 return (IXGBE_SUCCESS); 165 } 166 167 /* 168 * ixgbe_init_hw_generic - Generic hardware initialization 169 * @hw: pointer to hardware structure 170 * 171 * Initialize the hardware by resetting the hardware, filling the bus info 172 * structure and media type, clears all on chip counters, initializes receive 173 * address registers, multicast table, VLAN filter table, calls routine to set 174 * up link and flow control settings, and leaves transmit and receive units 175 * disabled and uninitialized 176 */ 177 s32 178 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 179 { 180 s32 status = IXGBE_SUCCESS; 181 182 DEBUGFUNC("ixgbe_init_hw_generic"); 183 184 /* Reset the hardware */ 185 status = hw->mac.ops.reset_hw(hw); 186 187 if (status == IXGBE_SUCCESS) { 188 /* Start the HW */ 189 status = hw->mac.ops.start_hw(hw); 190 } 191 192 return (status); 193 } 194 195 /* 196 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 197 * @hw: pointer to hardware structure 198 * 199 * Clears all hardware statistics counters by reading them from the hardware 200 * Statistics counters are clear on read. 201 */ 202 s32 203 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 204 { 205 u16 i = 0; 206 207 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 208 209 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS); 210 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC); 211 (void) IXGBE_READ_REG(hw, IXGBE_ERRBC); 212 (void) IXGBE_READ_REG(hw, IXGBE_MSPDC); 213 for (i = 0; i < 8; i++) 214 (void) IXGBE_READ_REG(hw, IXGBE_MPC(i)); 215 216 (void) IXGBE_READ_REG(hw, IXGBE_MLFC); 217 (void) IXGBE_READ_REG(hw, IXGBE_MRFC); 218 (void) IXGBE_READ_REG(hw, IXGBE_RLEC); 219 (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC); 220 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 221 if (hw->mac.type >= ixgbe_mac_82599EB) { 222 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 223 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 224 } else { 225 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC); 226 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 227 } 228 229 for (i = 0; i < 8; i++) { 230 (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 231 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 232 if (hw->mac.type >= ixgbe_mac_82599EB) { 233 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 234 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 235 } else { 236 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 237 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 238 } 239 } 240 if (hw->mac.type >= ixgbe_mac_82599EB) 241 for (i = 0; i < 8; i++) 242 (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 243 244 (void) IXGBE_READ_REG(hw, IXGBE_PRC64); 245 (void) IXGBE_READ_REG(hw, IXGBE_PRC127); 246 (void) IXGBE_READ_REG(hw, IXGBE_PRC255); 247 (void) IXGBE_READ_REG(hw, IXGBE_PRC511); 248 (void) IXGBE_READ_REG(hw, IXGBE_PRC1023); 249 (void) IXGBE_READ_REG(hw, IXGBE_PRC1522); 250 (void) IXGBE_READ_REG(hw, IXGBE_GPRC); 251 (void) IXGBE_READ_REG(hw, IXGBE_BPRC); 252 (void) IXGBE_READ_REG(hw, IXGBE_MPRC); 253 (void) IXGBE_READ_REG(hw, IXGBE_GPTC); 254 (void) IXGBE_READ_REG(hw, IXGBE_GORCL); 255 (void) IXGBE_READ_REG(hw, IXGBE_GORCH); 256 (void) IXGBE_READ_REG(hw, IXGBE_GOTCL); 257 (void) IXGBE_READ_REG(hw, IXGBE_GOTCH); 258 for (i = 0; i < 8; i++) 259 (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 260 (void) IXGBE_READ_REG(hw, IXGBE_RUC); 261 (void) IXGBE_READ_REG(hw, IXGBE_RFC); 262 (void) IXGBE_READ_REG(hw, IXGBE_ROC); 263 (void) IXGBE_READ_REG(hw, IXGBE_RJC); 264 (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC); 265 (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC); 266 (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC); 267 (void) IXGBE_READ_REG(hw, IXGBE_TORL); 268 (void) IXGBE_READ_REG(hw, IXGBE_TORH); 269 (void) IXGBE_READ_REG(hw, IXGBE_TPR); 270 (void) IXGBE_READ_REG(hw, IXGBE_TPT); 271 (void) IXGBE_READ_REG(hw, IXGBE_PTC64); 272 (void) IXGBE_READ_REG(hw, IXGBE_PTC127); 273 (void) IXGBE_READ_REG(hw, IXGBE_PTC255); 274 (void) IXGBE_READ_REG(hw, IXGBE_PTC511); 275 (void) IXGBE_READ_REG(hw, IXGBE_PTC1023); 276 (void) IXGBE_READ_REG(hw, IXGBE_PTC1522); 277 (void) IXGBE_READ_REG(hw, IXGBE_MPTC); 278 (void) IXGBE_READ_REG(hw, IXGBE_BPTC); 279 for (i = 0; i < 16; i++) { 280 (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 281 (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 282 (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 283 if (hw->mac.type >= ixgbe_mac_82599EB) { 284 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 285 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 286 } else { 287 (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 288 } 289 } 290 291 return (IXGBE_SUCCESS); 292 } 293 294 /* 295 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 296 * @hw: pointer to hardware structure 297 * @pba_num: stores the part number from the EEPROM 298 * 299 * Reads the part number from the EEPROM. 300 */ 301 s32 302 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 303 { 304 s32 ret_val; 305 u16 data; 306 307 DEBUGFUNC("ixgbe_read_pba_num_generic"); 308 309 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 310 if (ret_val) { 311 DEBUGOUT("NVM Read Error\n"); 312 return (ret_val); 313 } 314 *pba_num = (u32)(data << 16); 315 316 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 317 if (ret_val) { 318 DEBUGOUT("NVM Read Error\n"); 319 return (ret_val); 320 } 321 *pba_num |= data; 322 323 return (IXGBE_SUCCESS); 324 } 325 326 /* 327 * ixgbe_get_mac_addr_generic - Generic get MAC address 328 * @hw: pointer to hardware structure 329 * @mac_addr: Adapter MAC address 330 * 331 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 332 * A reset of the adapter must be performed prior to calling this function 333 * in order for the MAC address to have been loaded from the EEPROM into RAR0 334 */ 335 s32 336 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 337 { 338 u32 rar_high; 339 u32 rar_low; 340 u16 i; 341 342 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 343 344 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 345 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 346 347 for (i = 0; i < 4; i++) 348 mac_addr[i] = (u8)(rar_low >> (i*8)); 349 350 for (i = 0; i < 2; i++) 351 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 352 353 return (IXGBE_SUCCESS); 354 } 355 356 /* 357 * ixgbe_get_bus_info_generic - Generic set PCI bus info 358 * @hw: pointer to hardware structure 359 * 360 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 361 */ 362 s32 363 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 364 { 365 struct ixgbe_mac_info *mac = &hw->mac; 366 u16 link_status; 367 368 DEBUGFUNC("ixgbe_get_bus_info_generic"); 369 370 hw->bus.type = ixgbe_bus_type_pci_express; 371 372 /* Get the negotiated link width and speed from PCI config space */ 373 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 374 375 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 376 case IXGBE_PCI_LINK_WIDTH_1: 377 hw->bus.width = ixgbe_bus_width_pcie_x1; 378 break; 379 case IXGBE_PCI_LINK_WIDTH_2: 380 hw->bus.width = ixgbe_bus_width_pcie_x2; 381 break; 382 case IXGBE_PCI_LINK_WIDTH_4: 383 hw->bus.width = ixgbe_bus_width_pcie_x4; 384 break; 385 case IXGBE_PCI_LINK_WIDTH_8: 386 hw->bus.width = ixgbe_bus_width_pcie_x8; 387 break; 388 default: 389 hw->bus.width = ixgbe_bus_width_unknown; 390 break; 391 } 392 393 switch (link_status & IXGBE_PCI_LINK_SPEED) { 394 case IXGBE_PCI_LINK_SPEED_2500: 395 hw->bus.speed = ixgbe_bus_speed_2500; 396 break; 397 case IXGBE_PCI_LINK_SPEED_5000: 398 hw->bus.speed = ixgbe_bus_speed_5000; 399 break; 400 default: 401 hw->bus.speed = ixgbe_bus_speed_unknown; 402 break; 403 } 404 405 mac->ops.set_lan_id(hw); 406 407 return (IXGBE_SUCCESS); 408 } 409 410 411 /* 412 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 413 * @hw: pointer to the HW structure 414 * 415 * Determines the LAN function id by reading memory-mapped registers 416 * and swaps the port value if requested. 417 */ 418 void 419 ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 420 { 421 struct ixgbe_bus_info *bus = &hw->bus; 422 u32 reg; 423 424 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 425 426 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 427 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 428 bus->lan_id = bus->func; 429 430 /* check for a port swap */ 431 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 432 if (reg & IXGBE_FACTPS_LFS) 433 bus->func ^= 0x1; 434 } 435 436 /* 437 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 438 * @hw: pointer to hardware structure 439 * 440 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 441 * disables transmit and receive units. The adapter_stopped flag is used by 442 * the shared code and drivers to determine if the adapter is in a stopped 443 * state and should not touch the hardware. 444 */ 445 s32 446 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 447 { 448 u32 number_of_queues; 449 u32 reg_val; 450 u16 i; 451 452 DEBUGFUNC("ixgbe_stop_adapter_generic"); 453 454 /* 455 * Set the adapter_stopped flag so other driver functions stop touching 456 * the hardware 457 */ 458 hw->adapter_stopped = true; 459 460 /* Disable the receive unit */ 461 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 462 reg_val &= ~(IXGBE_RXCTRL_RXEN); 463 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 464 IXGBE_WRITE_FLUSH(hw); 465 msec_delay(2); 466 467 /* Clear interrupt mask to stop from interrupts being generated */ 468 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 469 470 /* Clear any pending interrupts */ 471 (void) IXGBE_READ_REG(hw, IXGBE_EICR); 472 473 /* Disable the transmit unit. Each queue must be disabled. */ 474 number_of_queues = hw->mac.max_tx_queues; 475 for (i = 0; i < number_of_queues; i++) { 476 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 477 if (reg_val & IXGBE_TXDCTL_ENABLE) { 478 reg_val &= ~IXGBE_TXDCTL_ENABLE; 479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 480 } 481 } 482 483 /* 484 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 485 * access and verify no pending requests 486 */ 487 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) { 488 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 489 } 490 491 return (IXGBE_SUCCESS); 492 } 493 494 /* 495 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 496 * @hw: pointer to hardware structure 497 * @index: led number to turn on 498 */ 499 s32 500 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 501 { 502 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 503 504 DEBUGFUNC("ixgbe_led_on_generic"); 505 506 /* To turn on the LED, set mode to ON. */ 507 led_reg &= ~IXGBE_LED_MODE_MASK(index); 508 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 509 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 510 IXGBE_WRITE_FLUSH(hw); 511 512 return (IXGBE_SUCCESS); 513 } 514 515 /* 516 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 517 * @hw: pointer to hardware structure 518 * @index: led number to turn off 519 */ 520 s32 521 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 522 { 523 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 524 525 DEBUGFUNC("ixgbe_led_off_generic"); 526 527 /* To turn off the LED, set mode to OFF. */ 528 led_reg &= ~IXGBE_LED_MODE_MASK(index); 529 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 530 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 531 IXGBE_WRITE_FLUSH(hw); 532 533 return (IXGBE_SUCCESS); 534 } 535 536 /* 537 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 538 * @hw: pointer to hardware structure 539 * 540 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 541 * ixgbe_hw struct in order to set up EEPROM access. 542 */ 543 s32 544 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 545 { 546 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 547 u32 eec; 548 u16 eeprom_size; 549 550 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 551 552 if (eeprom->type == ixgbe_eeprom_uninitialized) { 553 eeprom->type = ixgbe_eeprom_none; 554 /* 555 * Set default semaphore delay to 10ms which is a well 556 * tested value 557 */ 558 eeprom->semaphore_delay = 10; 559 560 /* 561 * Check for EEPROM present first. 562 * If not present leave as none 563 */ 564 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 565 if (eec & IXGBE_EEC_PRES) { 566 eeprom->type = ixgbe_eeprom_spi; 567 568 /* 569 * SPI EEPROM is assumed here. This code would need to 570 * change if a future EEPROM is not SPI. 571 */ 572 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 573 IXGBE_EEC_SIZE_SHIFT); 574 eeprom->word_size = 1 << (eeprom_size + 575 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); 576 } 577 578 if (eec & IXGBE_EEC_ADDR_SIZE) 579 eeprom->address_bits = 16; 580 else 581 eeprom->address_bits = 8; 582 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 583 "%d\n", eeprom->type, eeprom->word_size, 584 eeprom->address_bits); 585 } 586 587 return (IXGBE_SUCCESS); 588 } 589 590 /* 591 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 592 * @hw: pointer to hardware structure 593 * @offset: offset within the EEPROM to be written to 594 * @data: 16 bit word to be written to the EEPROM 595 * 596 * If ixgbe_eeprom_update_checksum is not called after this function, the 597 * EEPROM will most likely contain an invalid checksum. 598 */ 599 s32 600 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 601 { 602 s32 status; 603 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 604 605 DEBUGFUNC("ixgbe_write_eeprom_generic"); 606 607 hw->eeprom.ops.init_params(hw); 608 609 if (offset >= hw->eeprom.word_size) { 610 status = IXGBE_ERR_EEPROM; 611 goto out; 612 } 613 614 /* Prepare the EEPROM for writing */ 615 status = ixgbe_acquire_eeprom(hw); 616 617 if (status == IXGBE_SUCCESS) { 618 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 619 ixgbe_release_eeprom(hw); 620 status = IXGBE_ERR_EEPROM; 621 } 622 } 623 624 if (status == IXGBE_SUCCESS) { 625 ixgbe_standby_eeprom(hw); 626 627 /* Send the WRITE ENABLE command (8 bit opcode ) */ 628 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 629 IXGBE_EEPROM_OPCODE_BITS); 630 631 ixgbe_standby_eeprom(hw); 632 633 /* 634 * Some SPI eeproms use the 8th address bit embedded in the 635 * opcode 636 */ 637 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 638 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 639 640 /* Send the Write command (8-bit opcode + addr) */ 641 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 642 IXGBE_EEPROM_OPCODE_BITS); 643 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 644 hw->eeprom.address_bits); 645 646 /* Send the data */ 647 data = (data >> 8) | (data << 8); 648 ixgbe_shift_out_eeprom_bits(hw, data, 16); 649 ixgbe_standby_eeprom(hw); 650 651 /* Done with writing - release the EEPROM */ 652 ixgbe_release_eeprom(hw); 653 } 654 655 out: 656 return (status); 657 } 658 659 /* 660 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 661 * @hw: pointer to hardware structure 662 * @offset: offset within the EEPROM to be read 663 * @data: read 16 bit value from EEPROM 664 * 665 * Reads 16 bit value from EEPROM through bit-bang method 666 */ 667 s32 668 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 669 u16 *data) 670 { 671 s32 status; 672 u16 word_in; 673 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 674 675 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 676 677 hw->eeprom.ops.init_params(hw); 678 679 if (offset >= hw->eeprom.word_size) { 680 status = IXGBE_ERR_EEPROM; 681 goto out; 682 } 683 684 /* Prepare the EEPROM for reading */ 685 status = ixgbe_acquire_eeprom(hw); 686 687 if (status == IXGBE_SUCCESS) { 688 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 689 ixgbe_release_eeprom(hw); 690 status = IXGBE_ERR_EEPROM; 691 } 692 } 693 694 if (status == IXGBE_SUCCESS) { 695 ixgbe_standby_eeprom(hw); 696 697 /* 698 * Some SPI eeproms use the 8th address bit embedded in the 699 * opcode 700 */ 701 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 702 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 703 704 /* Send the READ command (opcode + addr) */ 705 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 706 IXGBE_EEPROM_OPCODE_BITS); 707 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 708 hw->eeprom.address_bits); 709 710 /* Read the data. */ 711 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 712 *data = (word_in >> 8) | (word_in << 8); 713 714 /* End this read operation */ 715 ixgbe_release_eeprom(hw); 716 } 717 718 out: 719 return (status); 720 } 721 722 /* 723 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 724 * @hw: pointer to hardware structure 725 * @offset: offset of word in the EEPROM to read 726 * @data: word read from the EEPROM 727 * 728 * Reads a 16 bit word from the EEPROM using the EERD register. 729 */ 730 s32 731 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 732 { 733 u32 eerd; 734 s32 status; 735 736 DEBUGFUNC("ixgbe_read_eerd_generic"); 737 738 hw->eeprom.ops.init_params(hw); 739 740 if (offset >= hw->eeprom.word_size) { 741 status = IXGBE_ERR_EEPROM; 742 goto out; 743 } 744 745 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) + 746 IXGBE_EEPROM_RW_REG_START; 747 748 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 749 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 750 751 if (status == IXGBE_SUCCESS) 752 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 753 IXGBE_EEPROM_RW_REG_DATA); 754 else 755 DEBUGOUT("Eeprom read timed out\n"); 756 757 out: 758 return (status); 759 } 760 761 /* 762 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 763 * @hw: pointer to hardware structure 764 * @ee_reg: EEPROM flag for polling 765 * 766 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 767 * read or write is done respectively. 768 */ 769 s32 770 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 771 { 772 u32 i; 773 u32 reg; 774 s32 status = IXGBE_ERR_EEPROM; 775 776 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 777 778 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 779 if (ee_reg == IXGBE_NVM_POLL_READ) 780 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 781 else 782 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 783 784 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 785 status = IXGBE_SUCCESS; 786 break; 787 } 788 usec_delay(5); 789 } 790 return (status); 791 } 792 793 /* 794 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 795 * @hw: pointer to hardware structure 796 * 797 * Prepares EEPROM for access using bit-bang method. This function should 798 * be called before issuing a command to the EEPROM. 799 */ 800 static s32 801 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 802 { 803 s32 status = IXGBE_SUCCESS; 804 u32 eec; 805 u32 i; 806 807 DEBUGFUNC("ixgbe_acquire_eeprom"); 808 809 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 810 status = IXGBE_ERR_SWFW_SYNC; 811 812 if (status == IXGBE_SUCCESS) { 813 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 814 815 /* Request EEPROM Access */ 816 eec |= IXGBE_EEC_REQ; 817 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 818 819 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 820 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 821 if (eec & IXGBE_EEC_GNT) 822 break; 823 usec_delay(5); 824 } 825 826 /* Release if grant not acquired */ 827 if (!(eec & IXGBE_EEC_GNT)) { 828 eec &= ~IXGBE_EEC_REQ; 829 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 830 DEBUGOUT("Could not acquire EEPROM grant\n"); 831 832 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 833 status = IXGBE_ERR_EEPROM; 834 } 835 } 836 837 /* Setup EEPROM for Read/Write */ 838 if (status == IXGBE_SUCCESS) { 839 /* Clear CS and SK */ 840 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 841 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 842 IXGBE_WRITE_FLUSH(hw); 843 usec_delay(1); 844 } 845 return (status); 846 } 847 848 /* 849 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 850 * @hw: pointer to hardware structure 851 * 852 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 853 */ 854 static s32 855 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 856 { 857 s32 status = IXGBE_ERR_EEPROM; 858 u32 timeout = 2000; 859 u32 i; 860 u32 swsm; 861 862 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 863 864 /* Get SMBI software semaphore between device drivers first */ 865 for (i = 0; i < timeout; i++) { 866 /* 867 * If the SMBI bit is 0 when we read it, then the bit will be 868 * set and we have the semaphore 869 */ 870 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 871 if (!(swsm & IXGBE_SWSM_SMBI)) { 872 status = IXGBE_SUCCESS; 873 break; 874 } 875 usec_delay(50); 876 } 877 878 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 879 if (status == IXGBE_SUCCESS) { 880 for (i = 0; i < timeout; i++) { 881 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 882 883 /* Set the SW EEPROM semaphore bit to request access */ 884 swsm |= IXGBE_SWSM_SWESMBI; 885 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 886 887 /* 888 * If we set the bit successfully then we got the 889 * semaphore. 890 */ 891 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 892 if (swsm & IXGBE_SWSM_SWESMBI) 893 break; 894 895 usec_delay(50); 896 } 897 898 /* 899 * Release semaphores and return error if SW EEPROM semaphore 900 * was not granted because we don't have access to the EEPROM 901 */ 902 if (i >= timeout) { 903 DEBUGOUT("SWESMBI Software EEPROM semaphore " 904 "not granted.\n"); 905 ixgbe_release_eeprom_semaphore(hw); 906 status = IXGBE_ERR_EEPROM; 907 } 908 } else { 909 DEBUGOUT("Software semaphore SMBI between device drivers " 910 "not granted.\n"); 911 } 912 913 return (status); 914 } 915 916 /* 917 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 918 * @hw: pointer to hardware structure 919 * 920 * This function clears hardware semaphore bits. 921 */ 922 static void 923 ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 924 { 925 u32 swsm; 926 927 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 928 929 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 930 931 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 932 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 933 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 934 IXGBE_WRITE_FLUSH(hw); 935 } 936 937 /* 938 * ixgbe_ready_eeprom - Polls for EEPROM ready 939 * @hw: pointer to hardware structure 940 */ 941 static s32 942 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 943 { 944 s32 status = IXGBE_SUCCESS; 945 u16 i; 946 u8 spi_stat_reg; 947 948 DEBUGFUNC("ixgbe_ready_eeprom"); 949 950 /* 951 * Read "Status Register" repeatedly until the LSB is cleared. The 952 * EEPROM will signal that the command has been completed by clearing 953 * bit 0 of the internal status register. If it's not cleared within 954 * 5 milliseconds, then error out. 955 */ 956 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 957 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 958 IXGBE_EEPROM_OPCODE_BITS); 959 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 960 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 961 break; 962 963 usec_delay(5); 964 ixgbe_standby_eeprom(hw); 965 }; 966 967 /* 968 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 969 * devices (and only 0-5mSec on 5V devices) 970 */ 971 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 972 DEBUGOUT("SPI EEPROM Status error\n"); 973 status = IXGBE_ERR_EEPROM; 974 } 975 976 return (status); 977 } 978 979 /* 980 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 981 * @hw: pointer to hardware structure 982 */ 983 static void 984 ixgbe_standby_eeprom(struct ixgbe_hw *hw) 985 { 986 u32 eec; 987 988 DEBUGFUNC("ixgbe_standby_eeprom"); 989 990 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 991 992 /* Toggle CS to flush commands */ 993 eec |= IXGBE_EEC_CS; 994 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 995 IXGBE_WRITE_FLUSH(hw); 996 usec_delay(1); 997 eec &= ~IXGBE_EEC_CS; 998 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 999 IXGBE_WRITE_FLUSH(hw); 1000 usec_delay(1); 1001 } 1002 1003 /* 1004 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1005 * @hw: pointer to hardware structure 1006 * @data: data to send to the EEPROM 1007 * @count: number of bits to shift out 1008 */ 1009 static void 1010 ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1011 u16 count) 1012 { 1013 u32 eec; 1014 u32 mask; 1015 u32 i; 1016 1017 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1018 1019 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1020 1021 /* 1022 * Mask is used to shift "count" bits of "data" out to the EEPROM 1023 * one bit at a time. Determine the starting bit based on count 1024 */ 1025 mask = 0x01 << (count - 1); 1026 1027 for (i = 0; i < count; i++) { 1028 /* 1029 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1030 * "1", and then raising and then lowering the clock (the SK 1031 * bit controls the clock input to the EEPROM). A "0" is 1032 * shifted out to the EEPROM by setting "DI" to "0" and then 1033 * raising and then lowering the clock. 1034 */ 1035 if (data & mask) 1036 eec |= IXGBE_EEC_DI; 1037 else 1038 eec &= ~IXGBE_EEC_DI; 1039 1040 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1041 IXGBE_WRITE_FLUSH(hw); 1042 1043 usec_delay(1); 1044 1045 ixgbe_raise_eeprom_clk(hw, &eec); 1046 ixgbe_lower_eeprom_clk(hw, &eec); 1047 1048 /* 1049 * Shift mask to signify next bit of data to shift in to the 1050 * EEPROM 1051 */ 1052 mask = mask >> 1; 1053 }; 1054 1055 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1056 eec &= ~IXGBE_EEC_DI; 1057 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1058 IXGBE_WRITE_FLUSH(hw); 1059 } 1060 1061 /* 1062 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1063 * @hw: pointer to hardware structure 1064 */ 1065 static u16 1066 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1067 { 1068 u32 eec; 1069 u32 i; 1070 u16 data = 0; 1071 1072 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 1073 1074 /* 1075 * In order to read a register from the EEPROM, we need to shift 1076 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1077 * the clock input to the EEPROM (setting the SK bit), and then reading 1078 * the value of the "DO" bit. During this "shifting in" process the 1079 * "DI" bit should always be clear. 1080 */ 1081 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1082 1083 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1084 1085 for (i = 0; i < count; i++) { 1086 data = data << 1; 1087 ixgbe_raise_eeprom_clk(hw, &eec); 1088 1089 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1090 1091 eec &= ~(IXGBE_EEC_DI); 1092 if (eec & IXGBE_EEC_DO) 1093 data |= 1; 1094 1095 ixgbe_lower_eeprom_clk(hw, &eec); 1096 } 1097 1098 return (data); 1099 } 1100 1101 /* 1102 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1103 * @hw: pointer to hardware structure 1104 * @eec: EEC register's current value 1105 */ 1106 static void 1107 ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1108 { 1109 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 1110 1111 /* 1112 * Raise the clock input to the EEPROM 1113 * (setting the SK bit), then delay 1114 */ 1115 *eec = *eec | IXGBE_EEC_SK; 1116 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1117 IXGBE_WRITE_FLUSH(hw); 1118 usec_delay(1); 1119 } 1120 1121 /* 1122 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1123 * @hw: pointer to hardware structure 1124 * @eecd: EECD's current value 1125 */ 1126 static void 1127 ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1128 { 1129 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 1130 1131 /* 1132 * Lower the clock input to the EEPROM (clearing the SK bit), then 1133 * delay 1134 */ 1135 *eec = *eec & ~IXGBE_EEC_SK; 1136 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1137 IXGBE_WRITE_FLUSH(hw); 1138 usec_delay(1); 1139 } 1140 1141 /* 1142 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1143 * @hw: pointer to hardware structure 1144 */ 1145 static void 1146 ixgbe_release_eeprom(struct ixgbe_hw *hw) 1147 { 1148 u32 eec; 1149 1150 DEBUGFUNC("ixgbe_release_eeprom"); 1151 1152 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1153 1154 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1155 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1156 1157 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1158 IXGBE_WRITE_FLUSH(hw); 1159 1160 usec_delay(1); 1161 1162 /* Stop requesting EEPROM access */ 1163 eec &= ~IXGBE_EEC_REQ; 1164 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1165 1166 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1167 1168 /* Delay before attempt to obtain semaphore again to allow FW access */ 1169 msec_delay(hw->eeprom.semaphore_delay); 1170 } 1171 1172 /* 1173 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1174 * @hw: pointer to hardware structure 1175 */ 1176 static u16 1177 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) 1178 { 1179 u16 i; 1180 u16 j; 1181 u16 checksum = 0; 1182 u16 length = 0; 1183 u16 pointer = 0; 1184 u16 word = 0; 1185 1186 DEBUGFUNC("ixgbe_calc_eeprom_checksum"); 1187 1188 /* Include 0x0-0x3F in the checksum */ 1189 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1190 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1191 DEBUGOUT("EEPROM read failed\n"); 1192 break; 1193 } 1194 checksum += word; 1195 } 1196 1197 /* Include all data from pointers except for the fw pointer */ 1198 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1199 hw->eeprom.ops.read(hw, i, &pointer); 1200 1201 /* Make sure the pointer seems valid */ 1202 if (pointer != 0xFFFF && pointer != 0) { 1203 hw->eeprom.ops.read(hw, pointer, &length); 1204 1205 if (length != 0xFFFF && length != 0) { 1206 for (j = pointer+1; j <= pointer+length; j++) { 1207 hw->eeprom.ops.read(hw, j, &word); 1208 checksum += word; 1209 } 1210 } 1211 } 1212 } 1213 1214 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1215 1216 return (checksum); 1217 } 1218 1219 /* 1220 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1221 * @hw: pointer to hardware structure 1222 * @checksum_val: calculated checksum 1223 * 1224 * Performs checksum calculation and validates the EEPROM checksum. If the 1225 * caller does not need checksum_val, the value can be NULL. 1226 */ 1227 s32 1228 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1229 u16 *checksum_val) 1230 { 1231 s32 status; 1232 u16 checksum; 1233 u16 read_checksum = 0; 1234 1235 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 1236 1237 /* 1238 * Read the first word from the EEPROM. If this times out or fails, do 1239 * not continue or we could be in for a very long wait while every 1240 * EEPROM read fails 1241 */ 1242 status = hw->eeprom.ops.read(hw, 0, &checksum); 1243 1244 if (status == IXGBE_SUCCESS) { 1245 checksum = ixgbe_calc_eeprom_checksum(hw); 1246 1247 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1248 1249 /* 1250 * Verify read checksum from EEPROM is the same as 1251 * calculated checksum 1252 */ 1253 if (read_checksum != checksum) 1254 status = IXGBE_ERR_EEPROM_CHECKSUM; 1255 1256 /* If the user cares, return the calculated checksum */ 1257 if (checksum_val) 1258 *checksum_val = checksum; 1259 } else { 1260 DEBUGOUT("EEPROM read failed\n"); 1261 } 1262 1263 return (status); 1264 } 1265 1266 /* 1267 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1268 * @hw: pointer to hardware structure 1269 */ 1270 s32 1271 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1272 { 1273 s32 status; 1274 u16 checksum; 1275 1276 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 1277 1278 /* 1279 * Read the first word from the EEPROM. If this times out or fails, do 1280 * not continue or we could be in for a very long wait while every 1281 * EEPROM read fails 1282 */ 1283 status = hw->eeprom.ops.read(hw, 0, &checksum); 1284 1285 if (status == IXGBE_SUCCESS) { 1286 checksum = ixgbe_calc_eeprom_checksum(hw); 1287 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1288 checksum); 1289 } else { 1290 DEBUGOUT("EEPROM read failed\n"); 1291 } 1292 1293 return (status); 1294 } 1295 1296 /* 1297 * ixgbe_validate_mac_addr - Validate MAC address 1298 * @mac_addr: pointer to MAC address. 1299 * 1300 * Tests a MAC address to ensure it is a valid Individual Address 1301 */ 1302 s32 1303 ixgbe_validate_mac_addr(u8 *mac_addr) 1304 { 1305 s32 status = IXGBE_SUCCESS; 1306 1307 DEBUGFUNC("ixgbe_validate_mac_addr"); 1308 1309 /* Make sure it is not a multicast address */ 1310 if (IXGBE_IS_MULTICAST(mac_addr)) { 1311 DEBUGOUT("MAC address is multicast\n"); 1312 status = IXGBE_ERR_INVALID_MAC_ADDR; 1313 /* Not a broadcast address */ 1314 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1315 DEBUGOUT("MAC address is broadcast\n"); 1316 status = IXGBE_ERR_INVALID_MAC_ADDR; 1317 /* Reject the zero address */ 1318 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1319 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1320 DEBUGOUT("MAC address is all zeros\n"); 1321 status = IXGBE_ERR_INVALID_MAC_ADDR; 1322 } 1323 return (status); 1324 } 1325 1326 /* 1327 * ixgbe_set_rar_generic - Set Rx address register 1328 * @hw: pointer to hardware structure 1329 * @index: Receive address register to write 1330 * @addr: Address to put into receive address register 1331 * @vmdq: VMDq "set" or "pool" index 1332 * @enable_addr: set flag that address is active 1333 * 1334 * Puts an ethernet address into a receive address register. 1335 */ 1336 s32 1337 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1338 u32 enable_addr) 1339 { 1340 u32 rar_low, rar_high; 1341 u32 rar_entries = hw->mac.num_rar_entries; 1342 1343 DEBUGFUNC("ixgbe_set_rar_generic"); 1344 1345 /* setup VMDq pool selection before this RAR gets enabled */ 1346 hw->mac.ops.set_vmdq(hw, index, vmdq); 1347 1348 /* Make sure we are using a valid rar index range */ 1349 if (index < rar_entries) { 1350 /* 1351 * HW expects these in little endian so we reverse the byte 1352 * order from network order (big endian) to little endian 1353 */ 1354 rar_low = ((u32)addr[0] | 1355 ((u32)addr[1] << 8) | 1356 ((u32)addr[2] << 16) | 1357 ((u32)addr[3] << 24)); 1358 /* 1359 * Some parts put the VMDq setting in the extra RAH bits, 1360 * so save everything except the lower 16 bits that hold part 1361 * of the address and the address valid bit. 1362 */ 1363 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1364 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1365 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1366 1367 if (enable_addr != 0) 1368 rar_high |= IXGBE_RAH_AV; 1369 1370 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1371 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1372 } else { 1373 DEBUGOUT1("RAR index %d is out of range.\n", index); 1374 } 1375 1376 return (IXGBE_SUCCESS); 1377 } 1378 1379 /* 1380 * ixgbe_clear_rar_generic - Remove Rx address register 1381 * @hw: pointer to hardware structure 1382 * @index: Receive address register to write 1383 * 1384 * Clears an ethernet address from a receive address register. 1385 */ 1386 s32 1387 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1388 { 1389 u32 rar_high; 1390 u32 rar_entries = hw->mac.num_rar_entries; 1391 1392 DEBUGFUNC("ixgbe_clear_rar_generic"); 1393 1394 /* Make sure we are using a valid rar index range */ 1395 if (index < rar_entries) { 1396 /* 1397 * Some parts put the VMDq setting in the extra RAH bits, 1398 * so save everything except the lower 16 bits that hold part 1399 * of the address and the address valid bit. 1400 */ 1401 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1402 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1403 1404 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1405 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1406 } else { 1407 DEBUGOUT1("RAR index %d is out of range.\n", index); 1408 } 1409 1410 /* clear VMDq pool/queue selection for this RAR */ 1411 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1412 1413 return (IXGBE_SUCCESS); 1414 } 1415 1416 /* 1417 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1418 * @hw: pointer to hardware structure 1419 * 1420 * Places the MAC address in receive address register 0 and clears the rest 1421 * of the receive address registers. Clears the multicast table. Assumes 1422 * the receiver is in reset when the routine is called. 1423 */ 1424 s32 1425 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1426 { 1427 u32 i; 1428 u32 rar_entries = hw->mac.num_rar_entries; 1429 1430 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 1431 1432 /* 1433 * If the current mac address is valid, assume it is a software override 1434 * to the permanent address. 1435 * Otherwise, use the permanent address from the eeprom. 1436 */ 1437 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1438 IXGBE_ERR_INVALID_MAC_ADDR) { 1439 /* Get the MAC address from the RAR0 for later reference */ 1440 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1441 1442 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1443 hw->mac.addr[0], hw->mac.addr[1], 1444 hw->mac.addr[2]); 1445 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1446 hw->mac.addr[4], hw->mac.addr[5]); 1447 } else { 1448 /* Setup the receive address. */ 1449 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1450 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1451 hw->mac.addr[0], hw->mac.addr[1], 1452 hw->mac.addr[2]); 1453 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1454 hw->mac.addr[4], hw->mac.addr[5]); 1455 1456 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1457 } 1458 hw->addr_ctrl.overflow_promisc = 0; 1459 1460 hw->addr_ctrl.rar_used_count = 1; 1461 1462 /* Zero out the other receive addresses. */ 1463 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1464 for (i = 1; i < rar_entries; i++) { 1465 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1466 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1467 } 1468 1469 /* Clear the MTA */ 1470 hw->addr_ctrl.mta_in_use = 0; 1471 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1472 1473 DEBUGOUT(" Clearing MTA\n"); 1474 for (i = 0; i < hw->mac.mcft_size; i++) 1475 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1476 1477 (void) ixgbe_init_uta_tables(hw); 1478 1479 return (IXGBE_SUCCESS); 1480 } 1481 1482 1483 /* 1484 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1485 * @hw: pointer to hardware structure 1486 * @addr: new address 1487 * 1488 * Adds it to unused receive address register or goes into promiscuous mode. 1489 */ 1490 void 1491 ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1492 { 1493 u32 rar_entries = hw->mac.num_rar_entries; 1494 u32 rar; 1495 1496 DEBUGFUNC("ixgbe_add_uc_addr"); 1497 1498 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1499 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1500 1501 /* 1502 * Place this address in the RAR if there is room, 1503 * else put the controller into promiscuous mode 1504 */ 1505 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1506 rar = hw->addr_ctrl.rar_used_count; 1507 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1508 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1509 hw->addr_ctrl.rar_used_count++; 1510 } else { 1511 hw->addr_ctrl.overflow_promisc++; 1512 } 1513 1514 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1515 } 1516 1517 /* 1518 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1519 * @hw: pointer to hardware structure 1520 * @addr_list: the list of new addresses 1521 * @addr_count: number of addresses 1522 * @next: iterator function to walk the address list 1523 * 1524 * The given list replaces any existing list. Clears the secondary addrs from 1525 * receive address registers. Uses unused receive address registers for the 1526 * first secondary addresses, and falls back to promiscuous mode as needed. 1527 * 1528 * Drivers using secondary unicast addresses must set user_set_promisc when 1529 * manually putting the device into promiscuous mode. 1530 */ 1531 s32 1532 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1533 u32 addr_count, ixgbe_mc_addr_itr next) 1534 { 1535 u8 *addr; 1536 u32 i; 1537 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1538 u32 uc_addr_in_use; 1539 u32 fctrl; 1540 u32 vmdq; 1541 1542 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 1543 1544 /* 1545 * Clear accounting of old secondary address list, 1546 * don't count RAR[0] 1547 */ 1548 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1549 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1550 hw->addr_ctrl.overflow_promisc = 0; 1551 1552 /* Zero out the other receive addresses */ 1553 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use); 1554 for (i = 1; i <= uc_addr_in_use; i++) { 1555 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1556 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1557 } 1558 1559 /* Add the new addresses */ 1560 for (i = 0; i < addr_count; i++) { 1561 DEBUGOUT(" Adding the secondary addresses:\n"); 1562 addr = next(hw, &addr_list, &vmdq); 1563 ixgbe_add_uc_addr(hw, addr, vmdq); 1564 } 1565 1566 if (hw->addr_ctrl.overflow_promisc) { 1567 /* enable promisc if not already in overflow or set by user */ 1568 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1569 DEBUGOUT(" Entering address overflow promisc mode\n"); 1570 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1571 fctrl |= IXGBE_FCTRL_UPE; 1572 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1573 } 1574 } else { 1575 /* only disable if set by overflow, not by user */ 1576 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1577 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1578 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1579 fctrl &= ~IXGBE_FCTRL_UPE; 1580 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1581 } 1582 } 1583 1584 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1585 return (IXGBE_SUCCESS); 1586 } 1587 1588 /* 1589 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1590 * @hw: pointer to hardware structure 1591 * @mc_addr: the multicast address 1592 * 1593 * Extracts the 12 bits, from a multicast address, to determine which 1594 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1595 * incoming rx multicast addresses, to determine the bit-vector to check in 1596 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1597 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1598 * to mc_filter_type. 1599 */ 1600 static s32 1601 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1602 { 1603 u32 vector = 0; 1604 1605 DEBUGFUNC("ixgbe_mta_vector"); 1606 1607 switch (hw->mac.mc_filter_type) { 1608 case 0: /* use bits [47:36] of the address */ 1609 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1610 break; 1611 case 1: /* use bits [46:35] of the address */ 1612 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1613 break; 1614 case 2: /* use bits [45:34] of the address */ 1615 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1616 break; 1617 case 3: /* use bits [43:32] of the address */ 1618 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1619 break; 1620 default: /* Invalid mc_filter_type */ 1621 DEBUGOUT("MC filter type param set incorrectly\n"); 1622 ASSERT(0); 1623 break; 1624 } 1625 1626 /* vector can only be 12-bits or boundary will be exceeded */ 1627 vector &= 0xFFF; 1628 return (vector); 1629 } 1630 1631 /* 1632 * ixgbe_set_mta - Set bit-vector in multicast table 1633 * @hw: pointer to hardware structure 1634 * @hash_value: Multicast address hash value 1635 * 1636 * Sets the bit-vector in the multicast table. 1637 */ 1638 void 1639 ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1640 { 1641 u32 vector; 1642 u32 vector_bit; 1643 u32 vector_reg; 1644 u32 mta_reg; 1645 1646 DEBUGFUNC("ixgbe_set_mta"); 1647 1648 hw->addr_ctrl.mta_in_use++; 1649 1650 vector = ixgbe_mta_vector(hw, mc_addr); 1651 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1652 1653 /* 1654 * The MTA is a register array of 128 32-bit registers. It is treated 1655 * like an array of 4096 bits. We want to set bit 1656 * BitArray[vector_value]. So we figure out what register the bit is 1657 * in, read it, OR in the new bit, then write back the new value. The 1658 * register is determined by the upper 7 bits of the vector value and 1659 * the bit within that register are determined by the lower 5 bits of 1660 * the value. 1661 */ 1662 vector_reg = (vector >> 5) & 0x7F; 1663 vector_bit = vector & 0x1F; 1664 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1665 mta_reg |= (1 << vector_bit); 1666 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1667 } 1668 1669 /* 1670 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1671 * @hw: pointer to hardware structure 1672 * @mc_addr_list: the list of new multicast addresses 1673 * @mc_addr_count: number of addresses 1674 * @next: iterator function to walk the multicast address list 1675 * 1676 * The given list replaces any existing list. Clears the MC addrs from receive 1677 * address registers and the multicast table. Uses unused receive address 1678 * registers for the first multicast addresses, and hashes the rest into the 1679 * multicast table. 1680 */ 1681 s32 1682 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1683 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1684 { 1685 u32 i; 1686 u32 vmdq; 1687 1688 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 1689 1690 /* 1691 * Set the new number of MC addresses that we are being requested to 1692 * use. 1693 */ 1694 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1695 hw->addr_ctrl.mta_in_use = 0; 1696 1697 /* Clear the MTA */ 1698 DEBUGOUT(" Clearing MTA\n"); 1699 for (i = 0; i < hw->mac.mcft_size; i++) 1700 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1701 1702 /* Add the new addresses */ 1703 for (i = 0; i < mc_addr_count; i++) { 1704 DEBUGOUT(" Adding the multicast addresses:\n"); 1705 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1706 } 1707 1708 /* Enable mta */ 1709 if (hw->addr_ctrl.mta_in_use > 0) 1710 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1711 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1712 1713 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1714 return (IXGBE_SUCCESS); 1715 } 1716 1717 /* 1718 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1719 * @hw: pointer to hardware structure 1720 * 1721 * Enables multicast address in RAR and the use of the multicast hash table. 1722 */ 1723 s32 1724 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1725 { 1726 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1727 1728 DEBUGFUNC("ixgbe_enable_mc_generic"); 1729 1730 if (a->mta_in_use > 0) 1731 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1732 hw->mac.mc_filter_type); 1733 1734 return (IXGBE_SUCCESS); 1735 } 1736 1737 /* 1738 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1739 * @hw: pointer to hardware structure 1740 * 1741 * Disables multicast address in RAR and the use of the multicast hash table. 1742 */ 1743 s32 1744 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1745 { 1746 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1747 1748 DEBUGFUNC("ixgbe_disable_mc_generic"); 1749 1750 if (a->mta_in_use > 0) 1751 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1752 1753 return (IXGBE_SUCCESS); 1754 } 1755 1756 /* 1757 * ixgbe_fc_enable_generic - Enable flow control 1758 * @hw: pointer to hardware structure 1759 * @packetbuf_num: packet buffer number (0-7) 1760 * 1761 * Enable flow control according to the current settings. 1762 */ 1763 s32 1764 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1765 { 1766 s32 ret_val = IXGBE_SUCCESS; 1767 u32 mflcn_reg, fccfg_reg; 1768 u32 reg; 1769 u32 rx_pba_size; 1770 1771 DEBUGFUNC("ixgbe_fc_enable_generic"); 1772 1773 /* Negotiate the fc mode to use */ 1774 ret_val = ixgbe_fc_autoneg(hw); 1775 if (ret_val) 1776 goto out; 1777 1778 /* Disable any previous flow control settings */ 1779 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1780 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1781 1782 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1783 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1784 1785 /* 1786 * The possible values of fc.current_mode are: 1787 * 0: Flow control is completely disabled 1788 * 1: Rx flow control is enabled (we can receive pause frames, 1789 * but not send pause frames). 1790 * 2: Tx flow control is enabled (we can send pause frames but 1791 * we do not support receiving pause frames). 1792 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1793 * other: Invalid. 1794 */ 1795 switch (hw->fc.current_mode) { 1796 case ixgbe_fc_none: 1797 /* 1798 * Flow control is disabled by software override or autoneg. 1799 * The code below will actually disable it in the HW. 1800 */ 1801 break; 1802 case ixgbe_fc_rx_pause: 1803 /* 1804 * Rx Flow control is enabled and Tx Flow control is 1805 * disabled by software override. Since there really 1806 * isn't a way to advertise that we are capable of RX 1807 * Pause ONLY, we will advertise that we support both 1808 * symmetric and asymmetric Rx PAUSE. Later, we will 1809 * disable the adapter's ability to send PAUSE frames. 1810 */ 1811 mflcn_reg |= IXGBE_MFLCN_RFCE; 1812 break; 1813 case ixgbe_fc_tx_pause: 1814 /* 1815 * Tx Flow control is enabled, and Rx Flow control is 1816 * disabled by software override. 1817 */ 1818 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1819 break; 1820 case ixgbe_fc_full: 1821 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1822 mflcn_reg |= IXGBE_MFLCN_RFCE; 1823 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1824 break; 1825 default: 1826 DEBUGOUT("Flow control param set incorrectly\n"); 1827 ret_val = IXGBE_ERR_CONFIG; 1828 goto out; 1829 } 1830 1831 /* Set 802.3x based flow control settings. */ 1832 mflcn_reg |= IXGBE_MFLCN_DPF; 1833 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1834 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1835 1836 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1837 /* Thresholds are different for link flow control when in DCB mode */ 1838 if (reg & IXGBE_MTQC_RT_ENA) { 1839 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 1840 1841 /* Always disable XON for LFC when in DCB mode */ 1842 reg = (rx_pba_size >> 5) & 0xFFE0; 1843 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); 1844 1845 reg = (rx_pba_size >> 2) & 0xFFE0; 1846 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1847 reg |= IXGBE_FCRTH_FCEN; 1848 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); 1849 } else { 1850 /* 1851 * Set up and enable Rx high/low water mark thresholds, 1852 * enable XON. 1853 */ 1854 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1855 if (hw->fc.send_xon) { 1856 IXGBE_WRITE_REG(hw, 1857 IXGBE_FCRTL_82599(packetbuf_num), 1858 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 1859 } else { 1860 IXGBE_WRITE_REG(hw, 1861 IXGBE_FCRTL_82599(packetbuf_num), 1862 hw->fc.low_water); 1863 } 1864 1865 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1866 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1867 } 1868 } 1869 1870 /* Configure pause time (2 TCs per register) */ 1871 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 1872 if ((packetbuf_num & 1) == 0) 1873 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1874 else 1875 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1876 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1877 1878 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1879 1880 out: 1881 return (ret_val); 1882 } 1883 1884 /* 1885 * ixgbe_fc_autoneg - Configure flow control 1886 * @hw: pointer to hardware structure 1887 * 1888 * Compares our advertised flow control capabilities to those advertised by 1889 * our link partner, and determines the proper flow control mode to use. 1890 */ 1891 s32 1892 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1893 { 1894 s32 ret_val = IXGBE_SUCCESS; 1895 ixgbe_link_speed speed; 1896 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1897 u32 links2, anlp1_reg, autoc_reg, links; 1898 bool link_up; 1899 1900 DEBUGFUNC("ixgbe_fc_autoneg"); 1901 1902 /* 1903 * AN should have completed when the cable was plugged in. 1904 * Look for reasons to bail out. Bail out if: 1905 * - FC autoneg is disabled, or if 1906 * - link is not up. 1907 * 1908 * Since we're being called from an LSC, link is already known to be up. 1909 * So use link_up_wait_to_complete=false. 1910 */ 1911 hw->mac.ops.check_link(hw, &speed, &link_up, false); 1912 1913 if (hw->fc.disable_fc_autoneg || (!link_up)) { 1914 hw->fc.fc_was_autonegged = false; 1915 hw->fc.current_mode = hw->fc.requested_mode; 1916 goto out; 1917 } 1918 1919 /* 1920 * On backplane, bail out if 1921 * - backplane autoneg was not completed, or if 1922 * - link partner is not AN enabled 1923 */ 1924 if (hw->phy.media_type == ixgbe_media_type_backplane) { 1925 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 1926 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 1927 if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) || 1928 ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) { 1929 hw->fc.fc_was_autonegged = false; 1930 hw->fc.current_mode = hw->fc.requested_mode; 1931 goto out; 1932 } 1933 } 1934 1935 /* 1936 * On multispeed fiber at 1g, bail out if 1937 * - link is up but AN did not complete, or if 1938 * - link is up and AN completed but timed out 1939 */ 1940 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { 1941 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1942 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1943 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1944 hw->fc.fc_was_autonegged = false; 1945 hw->fc.current_mode = hw->fc.requested_mode; 1946 goto out; 1947 } 1948 } 1949 1950 /* 1951 * Bail out on 1952 * - copper or CX4 adapters 1953 * - fiber adapters running at 10gig 1954 */ 1955 if ((hw->phy.media_type == ixgbe_media_type_copper) || 1956 (hw->phy.media_type == ixgbe_media_type_cx4) || 1957 ((hw->phy.media_type == ixgbe_media_type_fiber) && 1958 (speed == IXGBE_LINK_SPEED_10GB_FULL))) { 1959 hw->fc.fc_was_autonegged = false; 1960 hw->fc.current_mode = hw->fc.requested_mode; 1961 goto out; 1962 } 1963 1964 /* 1965 * Read the AN advertisement and LP ability registers and resolve 1966 * local flow control settings accordingly 1967 */ 1968 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1969 (hw->phy.media_type != ixgbe_media_type_backplane)) { 1970 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1971 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1972 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1973 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1974 /* 1975 * Now we need to check if the user selected Rx ONLY 1976 * of pause frames. In this case, we had to advertise 1977 * FULL flow control because we could not advertise RX 1978 * ONLY. Hence, we must now check to see if we need to 1979 * turn OFF the TRANSMISSION of PAUSE frames. 1980 */ 1981 if (hw->fc.requested_mode == ixgbe_fc_full) { 1982 hw->fc.current_mode = ixgbe_fc_full; 1983 DEBUGOUT("Flow Control = FULL.\n"); 1984 } else { 1985 hw->fc.current_mode = ixgbe_fc_rx_pause; 1986 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 1987 } 1988 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1989 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1990 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1991 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1992 hw->fc.current_mode = ixgbe_fc_tx_pause; 1993 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1994 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1995 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1996 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1997 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1998 hw->fc.current_mode = ixgbe_fc_rx_pause; 1999 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2000 } else { 2001 hw->fc.current_mode = ixgbe_fc_none; 2002 DEBUGOUT("Flow Control = NONE.\n"); 2003 } 2004 } 2005 2006 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2007 /* 2008 * Read the 10g AN autoc and LP ability registers and resolve 2009 * local flow control settings accordingly 2010 */ 2011 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2012 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2013 2014 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 2015 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { 2016 /* 2017 * Now we need to check if the user selected Rx ONLY 2018 * of pause frames. In this case, we had to advertise 2019 * FULL flow control because we could not advertise RX 2020 * ONLY. Hence, we must now check to see if we need to 2021 * turn OFF the TRANSMISSION of PAUSE frames. 2022 */ 2023 if (hw->fc.requested_mode == ixgbe_fc_full) { 2024 hw->fc.current_mode = ixgbe_fc_full; 2025 DEBUGOUT("Flow Control = FULL.\n"); 2026 } else { 2027 hw->fc.current_mode = ixgbe_fc_rx_pause; 2028 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2029 } 2030 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 2031 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 2032 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 2033 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 2034 hw->fc.current_mode = ixgbe_fc_tx_pause; 2035 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2036 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 2037 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 2038 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 2039 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 2040 hw->fc.current_mode = ixgbe_fc_rx_pause; 2041 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2042 } else { 2043 hw->fc.current_mode = ixgbe_fc_none; 2044 DEBUGOUT("Flow Control = NONE.\n"); 2045 } 2046 } 2047 /* Record that current_mode is the result of a successful autoneg */ 2048 hw->fc.fc_was_autonegged = true; 2049 2050 out: 2051 return (ret_val); 2052 } 2053 2054 /* 2055 * ixgbe_setup_fc - Set up flow control 2056 * @hw: pointer to hardware structure 2057 * 2058 * Called at init time to set up flow control. 2059 */ 2060 s32 2061 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 2062 { 2063 s32 ret_val = IXGBE_SUCCESS; 2064 u32 reg; 2065 2066 DEBUGFUNC("ixgbe_setup_fc"); 2067 2068 /* Validate the packetbuf configuration */ 2069 if (packetbuf_num < 0 || packetbuf_num > 7) { 2070 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 2071 " 0-7\n", packetbuf_num); 2072 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2073 goto out; 2074 } 2075 2076 /* 2077 * Validate the water mark configuration. Zero water marks are invalid 2078 * because it causes the controller to just blast out fc packets. 2079 */ 2080 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 2081 DEBUGOUT("Invalid water mark configuration\n"); 2082 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2083 goto out; 2084 } 2085 2086 /* 2087 * Validate the requested mode. Strict IEEE mode does not allow 2088 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 2089 */ 2090 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2091 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2092 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2093 goto out; 2094 } 2095 2096 /* 2097 * 10gig parts do not have a word in the EEPROM to determine the 2098 * default flow control setting, so we explicitly set it to full. 2099 */ 2100 if (hw->fc.requested_mode == ixgbe_fc_default) 2101 hw->fc.requested_mode = ixgbe_fc_full; 2102 2103 /* 2104 * Set up the 1G flow control advertisement registers so the HW will be 2105 * able to do fc autoneg once the cable is plugged in. If we end up 2106 * using 10g instead, this is harmless. 2107 */ 2108 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2109 2110 /* 2111 * The possible values of fc.requested_mode are: 2112 * 0: Flow control is completely disabled 2113 * 1: Rx flow control is enabled (we can receive pause frames, 2114 * but not send pause frames). 2115 * 2: Tx flow control is enabled (we can send pause frames but 2116 * we do not support receiving pause frames). 2117 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2118 * other: Invalid. 2119 */ 2120 switch (hw->fc.requested_mode) { 2121 case ixgbe_fc_none: 2122 /* Flow control completely disabled by software override. */ 2123 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2124 break; 2125 case ixgbe_fc_rx_pause: 2126 /* 2127 * Rx Flow control is enabled and Tx Flow control is 2128 * disabled by software override. Since there really 2129 * isn't a way to advertise that we are capable of RX 2130 * Pause ONLY, we will advertise that we support both 2131 * symmetric and asymmetric Rx PAUSE. Later, we will 2132 * disable the adapter's ability to send PAUSE frames. 2133 */ 2134 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2135 break; 2136 case ixgbe_fc_tx_pause: 2137 /* 2138 * Tx Flow control is enabled, and Rx Flow control is 2139 * disabled by software override. 2140 */ 2141 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 2142 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 2143 break; 2144 case ixgbe_fc_full: 2145 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2146 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2147 break; 2148 default: 2149 DEBUGOUT("Flow control param set incorrectly\n"); 2150 ret_val = IXGBE_ERR_CONFIG; 2151 goto out; 2152 } 2153 2154 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 2155 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 2156 2157 /* Disable AN timeout */ 2158 if (hw->fc.strict_ieee) 2159 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 2160 2161 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2162 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2163 2164 /* 2165 * Set up the 10G flow control advertisement registers so the HW 2166 * can do fc autoneg once the cable is plugged in. If we end up 2167 * using 1g instead, this is harmless. 2168 */ 2169 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2170 2171 /* 2172 * The possible values of fc.requested_mode are: 2173 * 0: Flow control is completely disabled 2174 * 1: Rx flow control is enabled (we can receive pause frames, 2175 * but not send pause frames). 2176 * 2: Tx flow control is enabled (we can send pause frames but 2177 * we do not support receiving pause frames). 2178 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2179 * other: Invalid. 2180 */ 2181 switch (hw->fc.requested_mode) { 2182 case ixgbe_fc_none: 2183 /* Flow control completely disabled by software override. */ 2184 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2185 break; 2186 case ixgbe_fc_rx_pause: 2187 /* 2188 * Rx Flow control is enabled and Tx Flow control is 2189 * disabled by software override. Since there really 2190 * isn't a way to advertise that we are capable of RX 2191 * Pause ONLY, we will advertise that we support both 2192 * symmetric and asymmetric Rx PAUSE. Later, we will 2193 * disable the adapter's ability to send PAUSE frames. 2194 */ 2195 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2196 break; 2197 case ixgbe_fc_tx_pause: 2198 /* 2199 * Tx Flow control is enabled, and Rx Flow control is 2200 * disabled by software override. 2201 */ 2202 reg |= (IXGBE_AUTOC_ASM_PAUSE); 2203 reg &= ~(IXGBE_AUTOC_SYM_PAUSE); 2204 break; 2205 case ixgbe_fc_full: 2206 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2207 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2208 break; 2209 default: 2210 DEBUGOUT("Flow control param set incorrectly\n"); 2211 ret_val = IXGBE_ERR_CONFIG; 2212 goto out; 2213 } 2214 /* 2215 * AUTOC restart handles negotiation of 1G and 10G. There is 2216 * no need to set the PCS1GCTL register. 2217 */ 2218 reg |= IXGBE_AUTOC_AN_RESTART; 2219 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); 2220 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2221 2222 out: 2223 return (ret_val); 2224 } 2225 2226 /* 2227 * ixgbe_disable_pcie_master - Disable PCI-express master access 2228 * @hw: pointer to hardware structure 2229 * 2230 * Disables PCI-Express master access and verifies there are no pending 2231 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2232 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2233 * is returned signifying master requests disabled. 2234 */ 2235 s32 2236 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2237 { 2238 u32 i; 2239 u32 reg_val; 2240 u32 number_of_queues; 2241 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2242 2243 DEBUGFUNC("ixgbe_disable_pcie_master"); 2244 2245 /* Disable the receive unit by stopping each queue */ 2246 number_of_queues = hw->mac.max_rx_queues; 2247 for (i = 0; i < number_of_queues; i++) { 2248 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2249 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2250 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2251 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2252 } 2253 } 2254 2255 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2256 reg_val |= IXGBE_CTRL_GIO_DIS; 2257 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2258 2259 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2260 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 2261 status = IXGBE_SUCCESS; 2262 break; 2263 } 2264 usec_delay(100); 2265 } 2266 2267 return (status); 2268 } 2269 2270 /* 2271 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2272 * @hw: pointer to hardware structure 2273 * @mask: Mask to specify which semaphore to acquire 2274 * 2275 * Acquires the SWFW semaphore thought the GSSR register for the specified 2276 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2277 */ 2278 s32 2279 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2280 { 2281 u32 gssr; 2282 u32 swmask = mask; 2283 u32 fwmask = mask << 5; 2284 s32 timeout = 200; 2285 2286 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 2287 2288 while (timeout) { 2289 /* 2290 * SW EEPROM semaphore bit is used for access to all 2291 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2292 */ 2293 if (ixgbe_get_eeprom_semaphore(hw)) 2294 return (IXGBE_ERR_SWFW_SYNC); 2295 2296 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2297 if (!(gssr & (fwmask | swmask))) 2298 break; 2299 2300 /* 2301 * Firmware currently using resource (fwmask) or other software 2302 * thread currently using resource (swmask) 2303 */ 2304 ixgbe_release_eeprom_semaphore(hw); 2305 msec_delay(5); 2306 timeout--; 2307 } 2308 2309 if (!timeout) { 2310 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2311 return (IXGBE_ERR_SWFW_SYNC); 2312 } 2313 2314 gssr |= swmask; 2315 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2316 2317 ixgbe_release_eeprom_semaphore(hw); 2318 return (IXGBE_SUCCESS); 2319 } 2320 2321 /* 2322 * ixgbe_release_swfw_sync - Release SWFW semaphore 2323 * @hw: pointer to hardware structure 2324 * @mask: Mask to specify which semaphore to release 2325 * 2326 * Releases the SWFW semaphore thought the GSSR register for the specified 2327 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2328 */ 2329 void 2330 ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2331 { 2332 u32 gssr; 2333 u32 swmask = mask; 2334 2335 DEBUGFUNC("ixgbe_release_swfw_sync"); 2336 2337 (void) ixgbe_get_eeprom_semaphore(hw); 2338 2339 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2340 gssr &= ~swmask; 2341 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2342 2343 ixgbe_release_eeprom_semaphore(hw); 2344 } 2345 2346 /* 2347 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2348 * @hw: pointer to hardware structure 2349 * @regval: register value to write to RXCTRL 2350 * 2351 * Enables the Rx DMA unit 2352 */ 2353 s32 2354 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2355 { 2356 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 2357 2358 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2359 2360 return (IXGBE_SUCCESS); 2361 } 2362 2363 /* 2364 * ixgbe_blink_led_start_generic - Blink LED based on index. 2365 * @hw: pointer to hardware structure 2366 * @index: led number to blink 2367 */ 2368 s32 2369 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2370 { 2371 ixgbe_link_speed speed = 0; 2372 bool link_up = 0; 2373 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2374 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2375 2376 DEBUGFUNC("ixgbe_blink_led_start_generic"); 2377 2378 /* 2379 * Link must be up to auto-blink the LEDs; 2380 * Force it if link is down. 2381 */ 2382 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2383 2384 if (!link_up) { 2385 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2386 autoc_reg |= IXGBE_AUTOC_FLU; 2387 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2388 msec_delay(10); 2389 } 2390 2391 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2392 led_reg |= IXGBE_LED_BLINK(index); 2393 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2394 IXGBE_WRITE_FLUSH(hw); 2395 2396 return (IXGBE_SUCCESS); 2397 } 2398 2399 /* 2400 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2401 * @hw: pointer to hardware structure 2402 * @index: led number to stop blinking 2403 */ 2404 s32 2405 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2406 { 2407 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2408 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2409 2410 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 2411 2412 autoc_reg &= ~IXGBE_AUTOC_FLU; 2413 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2414 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2415 2416 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2417 led_reg &= ~IXGBE_LED_BLINK(index); 2418 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2419 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2420 IXGBE_WRITE_FLUSH(hw); 2421 2422 return (IXGBE_SUCCESS); 2423 } 2424 2425 /* 2426 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2427 * @hw: pointer to hardware structure 2428 * @san_mac_offset: SAN MAC address offset 2429 * 2430 * This function will read the EEPROM location for the SAN MAC address 2431 * pointer, and returns the value at that location. This is used in both 2432 * get and set mac_addr routines. 2433 */ 2434 static s32 2435 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset) 2436 { 2437 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 2438 2439 /* 2440 * First read the EEPROM pointer to see if the MAC addresses are 2441 * available. 2442 */ 2443 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2444 2445 return (IXGBE_SUCCESS); 2446 } 2447 2448 /* 2449 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2450 * @hw: pointer to hardware structure 2451 * @san_mac_addr: SAN MAC address 2452 * 2453 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2454 * per-port, so set_lan_id() must be called before reading the addresses. 2455 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2456 * upon for non-SFP connections, so we must call it here. 2457 */ 2458 s32 2459 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2460 { 2461 u16 san_mac_data, san_mac_offset; 2462 u8 i; 2463 2464 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 2465 2466 /* 2467 * First read the EEPROM pointer to see if the MAC addresses are 2468 * available. If they're not, no point in calling set_lan_id() here. 2469 */ 2470 (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2471 2472 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2473 /* 2474 * No addresses available in this EEPROM. It's not an 2475 * error though, so just wipe the local address and return. 2476 */ 2477 for (i = 0; i < 6; i++) 2478 san_mac_addr[i] = 0xFF; 2479 2480 goto san_mac_addr_out; 2481 } 2482 2483 /* make sure we know which port we need to program */ 2484 hw->mac.ops.set_lan_id(hw); 2485 /* apply the port offset to the address offset */ 2486 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2487 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2488 for (i = 0; i < 3; i++) { 2489 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2490 san_mac_addr[i * 2] = (u8)(san_mac_data); 2491 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2492 san_mac_offset++; 2493 } 2494 2495 san_mac_addr_out: 2496 return (IXGBE_SUCCESS); 2497 } 2498 2499 /* 2500 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 2501 * @hw: pointer to hardware structure 2502 * @san_mac_addr: SAN MAC address 2503 * 2504 * Write a SAN MAC address to the EEPROM. 2505 */ 2506 s32 2507 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2508 { 2509 s32 status = IXGBE_SUCCESS; 2510 u16 san_mac_data, san_mac_offset; 2511 u8 i; 2512 2513 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 2514 2515 /* Look for SAN mac address pointer. If not defined, return */ 2516 (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2517 2518 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2519 status = IXGBE_ERR_NO_SAN_ADDR_PTR; 2520 goto san_mac_addr_out; 2521 } 2522 2523 /* Make sure we know which port we need to write */ 2524 hw->mac.ops.set_lan_id(hw); 2525 /* Apply the port offset to the address offset */ 2526 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2527 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2528 2529 for (i = 0; i < 3; i++) { 2530 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 2531 san_mac_data |= (u16)(san_mac_addr[i * 2]); 2532 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 2533 san_mac_offset++; 2534 } 2535 2536 san_mac_addr_out: 2537 return (status); 2538 } 2539 2540 /* 2541 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2542 * @hw: pointer to hardware structure 2543 * 2544 * Read PCIe configuration space, and get the MSI-X vector count from 2545 * the capabilities table. 2546 */ 2547 u32 2548 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2549 { 2550 u32 msix_count = 64; 2551 2552 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 2553 if (hw->mac.msix_vectors_from_pcie) { 2554 msix_count = IXGBE_READ_PCIE_WORD(hw, 2555 IXGBE_PCIE_MSIX_82599_CAPS); 2556 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2557 2558 /* 2559 * MSI-X count is zero-based in HW, so increment to give 2560 * proper value. 2561 */ 2562 msix_count++; 2563 } 2564 2565 return (msix_count); 2566 } 2567 2568 /* 2569 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 2570 * @hw: pointer to hardware structure 2571 * @addr: Address to put into receive address register 2572 * @vmdq: VMDq pool to assign 2573 * 2574 * Puts an ethernet address into a receive address register, or 2575 * finds the rar that it is aleady in; adds to the pool list 2576 */ 2577 s32 2578 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2579 { 2580 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 2581 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 2582 u32 rar; 2583 u32 rar_low, rar_high; 2584 u32 addr_low, addr_high; 2585 2586 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 2587 2588 /* swap bytes for HW little endian */ 2589 addr_low = addr[0] | (addr[1] << 8) 2590 | (addr[2] << 16) 2591 | (addr[3] << 24); 2592 addr_high = addr[4] | (addr[5] << 8); 2593 2594 /* 2595 * Either find the mac_id in rar or find the first empty space. 2596 * rar_highwater points to just after the highest currently used 2597 * rar in order to shorten the search. It grows when we add a new 2598 * rar to the top. 2599 */ 2600 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 2601 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 2602 2603 if (((IXGBE_RAH_AV & rar_high) == 0) && 2604 first_empty_rar == NO_EMPTY_RAR_FOUND) { 2605 first_empty_rar = rar; 2606 } else if ((rar_high & 0xFFFF) == addr_high) { 2607 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 2608 if (rar_low == addr_low) 2609 break; /* found it already in the rars */ 2610 } 2611 } 2612 2613 if (rar < hw->mac.rar_highwater) { 2614 /* already there so just add to the pool bits */ 2615 (void) ixgbe_set_vmdq(hw, rar, vmdq); 2616 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 2617 /* stick it into first empty RAR slot we found */ 2618 rar = first_empty_rar; 2619 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2620 } else if (rar == hw->mac.rar_highwater) { 2621 /* add it to the top of the list and inc the highwater mark */ 2622 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2623 hw->mac.rar_highwater++; 2624 } else if (rar >= hw->mac.num_rar_entries) { 2625 return (IXGBE_ERR_INVALID_MAC_ADDR); 2626 } 2627 2628 /* 2629 * If we found rar[0], make sure the default pool bit (we use pool 0) 2630 * remains cleared to be sure default pool packets will get delivered 2631 */ 2632 if (rar == 0) 2633 (void) ixgbe_clear_vmdq(hw, rar, 0); 2634 2635 return (rar); 2636 } 2637 2638 /* 2639 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2640 * @hw: pointer to hardware struct 2641 * @rar: receive address register index to disassociate 2642 * @vmdq: VMDq pool index to remove from the rar 2643 */ 2644 s32 2645 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2646 { 2647 u32 mpsar_lo, mpsar_hi; 2648 u32 rar_entries = hw->mac.num_rar_entries; 2649 2650 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 2651 2652 if (rar < rar_entries) { 2653 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2654 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2655 2656 if (!mpsar_lo && !mpsar_hi) 2657 goto done; 2658 2659 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2660 if (mpsar_lo) { 2661 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2662 mpsar_lo = 0; 2663 } 2664 if (mpsar_hi) { 2665 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2666 mpsar_hi = 0; 2667 } 2668 } else if (vmdq < 32) { 2669 mpsar_lo &= ~(1 << vmdq); 2670 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2671 } else { 2672 mpsar_hi &= ~(1 << (vmdq - 32)); 2673 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2674 } 2675 2676 /* was that the last pool using this rar? */ 2677 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2678 hw->mac.ops.clear_rar(hw, rar); 2679 } else { 2680 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2681 } 2682 2683 done: 2684 return (IXGBE_SUCCESS); 2685 } 2686 2687 /* 2688 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2689 * @hw: pointer to hardware struct 2690 * @rar: receive address register index to associate with a VMDq index 2691 * @vmdq: VMDq pool index 2692 */ 2693 s32 2694 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2695 { 2696 u32 mpsar; 2697 u32 rar_entries = hw->mac.num_rar_entries; 2698 2699 DEBUGFUNC("ixgbe_set_vmdq_generic"); 2700 2701 if (rar < rar_entries) { 2702 if (vmdq < 32) { 2703 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2704 mpsar |= 1 << vmdq; 2705 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2706 } else { 2707 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2708 mpsar |= 1 << (vmdq - 32); 2709 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2710 } 2711 } else { 2712 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2713 } 2714 return (IXGBE_SUCCESS); 2715 } 2716 2717 /* 2718 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2719 * @hw: pointer to hardware structure 2720 */ 2721 s32 2722 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2723 { 2724 int i; 2725 2726 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 2727 DEBUGOUT(" Clearing UTA\n"); 2728 2729 for (i = 0; i < 128; i++) 2730 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2731 2732 return (IXGBE_SUCCESS); 2733 } 2734 2735 /* 2736 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2737 * @hw: pointer to hardware structure 2738 * @vlan: VLAN id to write to VLAN filter 2739 * 2740 * return the VLVF index where this VLAN id should be placed 2741 * 2742 */ 2743 s32 2744 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 2745 { 2746 u32 bits = 0; 2747 u32 first_empty_slot = 0; 2748 s32 regindex; 2749 2750 /* 2751 * Search for the vlan id in the VLVF entries. Save off the first empty 2752 * slot found along the way 2753 */ 2754 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 2755 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 2756 if (!bits && !(first_empty_slot)) 2757 first_empty_slot = regindex; 2758 else if ((bits & 0x0FFF) == vlan) 2759 break; 2760 } 2761 2762 /* 2763 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 2764 * in the VLVF. Else use the first empty VLVF register for this 2765 * vlan id. 2766 */ 2767 if (regindex >= IXGBE_VLVF_ENTRIES) { 2768 if (first_empty_slot) 2769 regindex = first_empty_slot; 2770 else { 2771 DEBUGOUT("No space in VLVF.\n"); 2772 regindex = -1; 2773 } 2774 } 2775 2776 return (regindex); 2777 } 2778 2779 /* 2780 * ixgbe_set_vfta_generic - Set VLAN filter table 2781 * @hw: pointer to hardware structure 2782 * @vlan: VLAN id to write to VLAN filter 2783 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2784 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2785 * 2786 * Turn on/off specified VLAN in the VLAN filter table. 2787 */ 2788 s32 2789 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 2790 { 2791 s32 regindex; 2792 u32 bitindex; 2793 u32 bits; 2794 u32 vt; 2795 2796 DEBUGFUNC("ixgbe_set_vfta_generic"); 2797 2798 if (vlan > 4095) 2799 return (IXGBE_ERR_PARAM); 2800 2801 /* 2802 * this is a 2 part operation - first the VFTA, then the 2803 * VLVF and VLVFB if VT Mode is set 2804 */ 2805 2806 /* 2807 * Part 1 2808 * The VFTA is a bitstring made up of 128 32-bit registers 2809 * that enable the particular VLAN id, much like the MTA: 2810 * bits[11-5]: which register 2811 * bits[4-0]: which bit in the register 2812 */ 2813 regindex = (vlan >> 5) & 0x7F; 2814 bitindex = vlan & 0x1F; 2815 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 2816 if (vlan_on) 2817 bits |= (1 << bitindex); 2818 else 2819 bits &= ~(1 << bitindex); 2820 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 2821 2822 2823 /* 2824 * Part 2 2825 * If VT Mode is set 2826 * Either vlan_on 2827 * make sure the vlan is in VLVF 2828 * set the vind bit in the matching VLVFB 2829 * Or !vlan_on 2830 * clear the pool bit and possibly the vind 2831 */ 2832 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2833 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 2834 if (vlan == 0) { 2835 regindex = 0; 2836 } else { 2837 regindex = ixgbe_find_vlvf_slot(hw, vlan); 2838 if (regindex < 0) 2839 goto out; 2840 } 2841 2842 if (vlan_on) { 2843 /* set the pool bit */ 2844 if (vind < 32) { 2845 bits = IXGBE_READ_REG(hw, 2846 IXGBE_VLVFB(regindex*2)); 2847 bits |= (1 << vind); 2848 IXGBE_WRITE_REG(hw, 2849 IXGBE_VLVFB(regindex*2), 2850 bits); 2851 } else { 2852 bits = IXGBE_READ_REG(hw, 2853 IXGBE_VLVFB((regindex*2)+1)); 2854 bits |= (1 << vind); 2855 IXGBE_WRITE_REG(hw, 2856 IXGBE_VLVFB((regindex*2)+1), 2857 bits); 2858 } 2859 } else { 2860 /* clear the pool bit */ 2861 if (vind < 32) { 2862 bits = IXGBE_READ_REG(hw, 2863 IXGBE_VLVFB(regindex*2)); 2864 bits &= ~(1 << vind); 2865 IXGBE_WRITE_REG(hw, 2866 IXGBE_VLVFB(regindex*2), 2867 bits); 2868 bits |= IXGBE_READ_REG(hw, 2869 IXGBE_VLVFB((regindex*2)+1)); 2870 } else { 2871 bits = IXGBE_READ_REG(hw, 2872 IXGBE_VLVFB((regindex*2)+1)); 2873 bits &= ~(1 << vind); 2874 IXGBE_WRITE_REG(hw, 2875 IXGBE_VLVFB((regindex*2)+1), 2876 bits); 2877 bits |= IXGBE_READ_REG(hw, 2878 IXGBE_VLVFB(regindex*2)); 2879 } 2880 } 2881 2882 if (bits) 2883 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 2884 (IXGBE_VLVF_VIEN | vlan)); 2885 else 2886 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0); 2887 } 2888 out: 2889 return (IXGBE_SUCCESS); 2890 } 2891 2892 /* 2893 * ixgbe_clear_vfta_generic - Clear VLAN filter table 2894 * @hw: pointer to hardware structure 2895 * 2896 * Clears the VLAN filer table, and the VMDq index associated with the filter 2897 */ 2898 s32 2899 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 2900 { 2901 u32 offset; 2902 2903 DEBUGFUNC("ixgbe_clear_vfta_generic"); 2904 2905 for (offset = 0; offset < hw->mac.vft_size; offset++) 2906 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 2907 2908 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 2909 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 2910 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 2911 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 2912 } 2913 2914 return (IXGBE_SUCCESS); 2915 } 2916 2917 /* 2918 * ixgbe_check_mac_link_generic - Determine link and speed status 2919 * @hw: pointer to hardware structure 2920 * @speed: pointer to link speed 2921 * @link_up: true when link is up 2922 * @link_up_wait_to_complete: bool used to wait for link up or not 2923 * 2924 * Reads the links register to determine if link is up and the current speed 2925 */ 2926 s32 2927 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 2928 bool *link_up, bool link_up_wait_to_complete) 2929 { 2930 u32 links_reg; 2931 u32 i; 2932 2933 DEBUGFUNC("ixgbe_check_mac_link_generic"); 2934 2935 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2936 if (link_up_wait_to_complete) { 2937 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 2938 if (links_reg & IXGBE_LINKS_UP) { 2939 *link_up = true; 2940 break; 2941 } else { 2942 *link_up = false; 2943 } 2944 msec_delay(100); 2945 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2946 } 2947 } else { 2948 if (links_reg & IXGBE_LINKS_UP) 2949 *link_up = true; 2950 else 2951 *link_up = false; 2952 } 2953 2954 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2955 IXGBE_LINKS_SPEED_10G_82599) 2956 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2957 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2958 IXGBE_LINKS_SPEED_1G_82599) 2959 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2960 else 2961 *speed = IXGBE_LINK_SPEED_100_FULL; 2962 2963 /* if link is down, zero out the current_mode */ 2964 if (*link_up == false) { 2965 hw->fc.current_mode = ixgbe_fc_none; 2966 hw->fc.fc_was_autonegged = false; 2967 } 2968 2969 return (IXGBE_SUCCESS); 2970 } 2971 2972 /* 2973 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 2974 * the EEPROM 2975 * @hw: pointer to hardware structure 2976 * @wwnn_prefix: the alternative WWNN prefix 2977 * @wwpn_prefix: the alternative WWPN prefix 2978 * 2979 * This function will read the EEPROM from the alternative SAN MAC address 2980 * block to check the support for the alternative WWNN/WWPN prefix support. 2981 */ 2982 s32 2983 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 2984 u16 *wwpn_prefix) 2985 { 2986 u16 offset, caps; 2987 u16 alt_san_mac_blk_offset; 2988 2989 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 2990 2991 /* clear output first */ 2992 *wwnn_prefix = 0xFFFF; 2993 *wwpn_prefix = 0xFFFF; 2994 2995 /* check if alternative SAN MAC is supported */ 2996 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 2997 &alt_san_mac_blk_offset); 2998 2999 if ((alt_san_mac_blk_offset == 0) || 3000 (alt_san_mac_blk_offset == 0xFFFF)) 3001 goto wwn_prefix_out; 3002 3003 /* check capability in alternative san mac address block */ 3004 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3005 hw->eeprom.ops.read(hw, offset, &caps); 3006 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3007 goto wwn_prefix_out; 3008 3009 /* get the corresponding prefix for WWNN/WWPN */ 3010 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3011 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3012 3013 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3014 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3015 3016 wwn_prefix_out: 3017 return (IXGBE_SUCCESS); 3018 } 3019
Indexes created Wed Nov 25 10:59:19 UTC 2009
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