1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #include "ixgbe_sw.h" 30 #include "ixgbe_debug.h" 31 32 #ifdef IXGBE_DEBUG 33 extern ddi_device_acc_attr_t ixgbe_regs_acc_attr; 34 35 /* 36 * Dump interrupt-related registers & structures 37 */ 38 void 39 ixgbe_dump_interrupt(void *adapter, char *tag) 40 { 41 ixgbe_t *ixgbe = (ixgbe_t *)adapter; 42 struct ixgbe_hw *hw = &ixgbe->hw; 43 ixgbe_intr_vector_t *vect; 44 uint32_t ivar, reg; 45 int i, j; 46 47 /* 48 * interrupt control registers 49 */ 50 ixgbe_log(ixgbe, "interrupt: %s\n", tag); 51 ixgbe_log(ixgbe, "..eims: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIMS)); 52 ixgbe_log(ixgbe, "..eimc: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIMC)); 53 ixgbe_log(ixgbe, "..eiac: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIAC)); 54 ixgbe_log(ixgbe, "..eiam: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIAM)); 55 ixgbe_log(ixgbe, "..gpie: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_GPIE)); 56 ixgbe_log(ixgbe, "otherflag: 0x%x\n", ixgbe->capab->other_intr); 57 ixgbe_log(ixgbe, "eims_mask: 0x%x\n", ixgbe->eims); 58 59 /* ivar: interrupt vector allocation registers */ 60 for (i = 0; i < IXGBE_IVAR_REG_NUM; i++) { 61 if (ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(i))) { 62 ixgbe_log(ixgbe, "ivar[%d]: 0x%x\n", i, ivar); 63 } 64 } 65 66 /* each allocated vector */ 67 for (i = 0; i < ixgbe->intr_cnt; i++) { 68 vect = &ixgbe->vect_map[i]; 69 ixgbe_log(ixgbe, 70 "vector %d rx rings %d tx rings %d eitr: 0x%x\n", 71 i, vect->rxr_cnt, vect->txr_cnt, 72 IXGBE_READ_REG(hw, IXGBE_EITR(i))); 73 74 /* for each rx ring bit set */ 75 j = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1)); 76 while (j >= 0) { 77 ixgbe_log(ixgbe, "rx %d ivar %d rxdctl: 0x%x srrctl: 0x%x\n", 78 j, IXGBE_IVAR_RX_QUEUE(j), 79 IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)), 80 IXGBE_READ_REG(hw, IXGBE_SRRCTL(j))); 81 j = bt_getlowbit(vect->rx_map, (j + 1), 82 (ixgbe->num_rx_rings - 1)); 83 } 84 85 /* for each tx ring bit set */ 86 j = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1)); 87 while (j >= 0) { 88 ixgbe_log(ixgbe, "tx %d ivar %d txdctl: 0x%x\n", 89 j, IXGBE_IVAR_TX_QUEUE(j), 90 IXGBE_READ_REG(hw, IXGBE_TXDCTL(j))); 91 j = bt_getlowbit(vect->tx_map, (j + 1), 92 (ixgbe->num_tx_rings - 1)); 93 } 94 } 95 96 /* reta: RSS redirection table */ 97 for (i = 0; i < 32; i++) { 98 ixgbe_log(ixgbe, "reta(%d): 0x%x\n", 99 i, IXGBE_READ_REG(hw, IXGBE_RETA(i))); 100 } 101 102 /* rssrk: RSS random key */ 103 for (i = 0; i < 10; i++) { 104 ixgbe_log(ixgbe, "rssrk(%d): 0x%x\n", 105 i, IXGBE_READ_REG(hw, IXGBE_RSSRK(i))); 106 } 107 108 /* check ral/rah */ 109 ixgbe_log(ixgbe, "-- ral/rah --\n"); 110 for (i = 0; i < 16; i++) { 111 if (reg = IXGBE_READ_REG(hw, IXGBE_RAL(i))) { 112 ixgbe_log(ixgbe, "ral(%d): 0x%x rah(%d): 0x%x\n", 113 i, reg, i, IXGBE_READ_REG(hw, IXGBE_RAH(i))); 114 } 115 } 116 117 /* check mta */ 118 ixgbe_log(ixgbe, "-- mta --\n"); 119 for (i = 0; i < 128; i++) { 120 if (reg = IXGBE_READ_REG(hw, IXGBE_MTA(i))) { 121 ixgbe_log(ixgbe, "mta(%d): 0x%x\n", i, reg); 122 } 123 } 124 125 /* check vfta */ 126 { 127 uint32_t off = IXGBE_VFTA(0); 128 ixgbe_log(ixgbe, "-- vfta --\n"); 129 for (i = 0; i < 640; i++) { 130 if (reg = IXGBE_READ_REG(hw, off)) { 131 ixgbe_log(ixgbe, "vfta(0x%x): 0x%x\n", off, reg); 132 } 133 off += 4; 134 } 135 } 136 137 /* check mdef */ 138 ixgbe_log(ixgbe, "-- mdef --\n"); 139 for (i = 0; i < 8; i++) { 140 if (reg = IXGBE_READ_REG(hw, IXGBE_MDEF(i))) { 141 ixgbe_log(ixgbe, "mdef(%d): 0x%x\n", i, reg); 142 } 143 } 144 } 145 146 /* 147 * Dump an ethernet address 148 */ 149 void 150 ixgbe_dump_addr(void *adapter, char *tag, const uint8_t *addr) 151 { 152 ixgbe_t *ixgbe = (ixgbe_t *)adapter; 153 char form[25]; 154 155 (void) sprintf(form, "%02x:%02x:%02x:%02x:%02x:%02x", 156 *addr, *(addr + 1), *(addr + 2), 157 *(addr + 3), *(addr + 4), *(addr + 5)); 158 159 ixgbe_log(ixgbe, "%s %s\n", tag, form); 160 } 161 162 void 163 ixgbe_pci_dump(void *arg) 164 { 165 ixgbe_t *ixgbe = (ixgbe_t *)arg; 166 ddi_acc_handle_t handle; 167 uint8_t cap_ptr; 168 uint8_t next_ptr; 169 uint32_t msix_bar; 170 uint32_t msix_ctrl; 171 uint32_t msix_tbl_sz; 172 uint32_t tbl_offset; 173 uint32_t tbl_bir; 174 uint32_t pba_offset; 175 uint32_t pba_bir; 176 off_t offset; 177 off_t mem_size; 178 uintptr_t base; 179 ddi_acc_handle_t acc_hdl; 180 int i; 181 182 handle = ixgbe->osdep.cfg_handle; 183 184 ixgbe_log(ixgbe, "Begin dump PCI config space"); 185 186 ixgbe_log(ixgbe, 187 "PCI_CONF_VENID:\t0x%x\n", 188 pci_config_get16(handle, PCI_CONF_VENID)); 189 ixgbe_log(ixgbe, 190 "PCI_CONF_DEVID:\t0x%x\n", 191 pci_config_get16(handle, PCI_CONF_DEVID)); 192 ixgbe_log(ixgbe, 193 "PCI_CONF_COMMAND:\t0x%x\n", 194 pci_config_get16(handle, PCI_CONF_COMM)); 195 ixgbe_log(ixgbe, 196 "PCI_CONF_STATUS:\t0x%x\n", 197 pci_config_get16(handle, PCI_CONF_STAT)); 198 ixgbe_log(ixgbe, 199 "PCI_CONF_REVID:\t0x%x\n", 200 pci_config_get8(handle, PCI_CONF_REVID)); 201 ixgbe_log(ixgbe, 202 "PCI_CONF_PROG_CLASS:\t0x%x\n", 203 pci_config_get8(handle, PCI_CONF_PROGCLASS)); 204 ixgbe_log(ixgbe, 205 "PCI_CONF_SUB_CLASS:\t0x%x\n", 206 pci_config_get8(handle, PCI_CONF_SUBCLASS)); 207 ixgbe_log(ixgbe, 208 "PCI_CONF_BAS_CLASS:\t0x%x\n", 209 pci_config_get8(handle, PCI_CONF_BASCLASS)); 210 ixgbe_log(ixgbe, 211 "PCI_CONF_CACHE_LINESZ:\t0x%x\n", 212 pci_config_get8(handle, PCI_CONF_CACHE_LINESZ)); 213 ixgbe_log(ixgbe, 214 "PCI_CONF_LATENCY_TIMER:\t0x%x\n", 215 pci_config_get8(handle, PCI_CONF_LATENCY_TIMER)); 216 ixgbe_log(ixgbe, 217 "PCI_CONF_HEADER_TYPE:\t0x%x\n", 218 pci_config_get8(handle, PCI_CONF_HEADER)); 219 ixgbe_log(ixgbe, 220 "PCI_CONF_BIST:\t0x%x\n", 221 pci_config_get8(handle, PCI_CONF_BIST)); 222 ixgbe_log(ixgbe, 223 "PCI_CONF_BASE0:\t0x%x\n", 224 pci_config_get32(handle, PCI_CONF_BASE0)); 225 ixgbe_log(ixgbe, 226 "PCI_CONF_BASE1:\t0x%x\n", 227 pci_config_get32(handle, PCI_CONF_BASE1)); 228 ixgbe_log(ixgbe, 229 "PCI_CONF_BASE2:\t0x%x\n", 230 pci_config_get32(handle, PCI_CONF_BASE2)); 231 232 /* MSI-X BAR */ 233 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); 234 ixgbe_log(ixgbe, 235 "PCI_CONF_BASE3:\t0x%x\n", msix_bar); 236 237 ixgbe_log(ixgbe, 238 "PCI_CONF_BASE4:\t0x%x\n", 239 pci_config_get32(handle, PCI_CONF_BASE4)); 240 ixgbe_log(ixgbe, 241 "PCI_CONF_BASE5:\t0x%x\n", 242 pci_config_get32(handle, PCI_CONF_BASE5)); 243 ixgbe_log(ixgbe, 244 "PCI_CONF_CIS:\t0x%x\n", 245 pci_config_get32(handle, PCI_CONF_CIS)); 246 ixgbe_log(ixgbe, 247 "PCI_CONF_SUBVENID:\t0x%x\n", 248 pci_config_get16(handle, PCI_CONF_SUBVENID)); 249 ixgbe_log(ixgbe, 250 "PCI_CONF_SUBSYSID:\t0x%x\n", 251 pci_config_get16(handle, PCI_CONF_SUBSYSID)); 252 ixgbe_log(ixgbe, 253 "PCI_CONF_ROM:\t0x%x\n", 254 pci_config_get32(handle, PCI_CONF_ROM)); 255 256 cap_ptr = pci_config_get8(handle, PCI_CONF_CAP_PTR); 257 258 ixgbe_log(ixgbe, 259 "PCI_CONF_CAP_PTR:\t0x%x\n", cap_ptr); 260 ixgbe_log(ixgbe, 261 "PCI_CONF_ILINE:\t0x%x\n", 262 pci_config_get8(handle, PCI_CONF_ILINE)); 263 ixgbe_log(ixgbe, 264 "PCI_CONF_IPIN:\t0x%x\n", 265 pci_config_get8(handle, PCI_CONF_IPIN)); 266 ixgbe_log(ixgbe, 267 "PCI_CONF_MIN_G:\t0x%x\n", 268 pci_config_get8(handle, PCI_CONF_MIN_G)); 269 ixgbe_log(ixgbe, 270 "PCI_CONF_MAX_L:\t0x%x\n", 271 pci_config_get8(handle, PCI_CONF_MAX_L)); 272 273 /* Power Management */ 274 offset = cap_ptr; 275 276 ixgbe_log(ixgbe, 277 "PCI_PM_CAP_ID:\t0x%x\n", 278 pci_config_get8(handle, offset)); 279 280 next_ptr = pci_config_get8(handle, offset + 1); 281 282 ixgbe_log(ixgbe, 283 "PCI_PM_NEXT_PTR:\t0x%x\n", next_ptr); 284 ixgbe_log(ixgbe, 285 "PCI_PM_CAP:\t0x%x\n", 286 pci_config_get16(handle, offset + PCI_PMCAP)); 287 ixgbe_log(ixgbe, 288 "PCI_PM_CSR:\t0x%x\n", 289 pci_config_get16(handle, offset + PCI_PMCSR)); 290 ixgbe_log(ixgbe, 291 "PCI_PM_CSR_BSE:\t0x%x\n", 292 pci_config_get8(handle, offset + PCI_PMCSR_BSE)); 293 ixgbe_log(ixgbe, 294 "PCI_PM_DATA:\t0x%x\n", 295 pci_config_get8(handle, offset + PCI_PMDATA)); 296 297 /* MSI Configuration */ 298 offset = next_ptr; 299 300 ixgbe_log(ixgbe, 301 "PCI_MSI_CAP_ID:\t0x%x\n", 302 pci_config_get8(handle, offset)); 303 304 next_ptr = pci_config_get8(handle, offset + 1); 305 306 ixgbe_log(ixgbe, 307 "PCI_MSI_NEXT_PTR:\t0x%x\n", next_ptr); 308 ixgbe_log(ixgbe, 309 "PCI_MSI_CTRL:\t0x%x\n", 310 pci_config_get16(handle, offset + PCI_MSI_CTRL)); 311 ixgbe_log(ixgbe, 312 "PCI_MSI_ADDR:\t0x%x\n", 313 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET)); 314 ixgbe_log(ixgbe, 315 "PCI_MSI_ADDR_HI:\t0x%x\n", 316 pci_config_get32(handle, offset + 0x8)); 317 ixgbe_log(ixgbe, 318 "PCI_MSI_DATA:\t0x%x\n", 319 pci_config_get16(handle, offset + 0xC)); 320 321 /* MSI-X Configuration */ 322 offset = next_ptr; 323 324 ixgbe_log(ixgbe, 325 "PCI_MSIX_CAP_ID:\t0x%x\n", 326 pci_config_get8(handle, offset)); 327 328 next_ptr = pci_config_get8(handle, offset + 1); 329 ixgbe_log(ixgbe, 330 "PCI_MSIX_NEXT_PTR:\t0x%x\n", next_ptr); 331 332 msix_ctrl = pci_config_get16(handle, offset + PCI_MSIX_CTRL); 333 msix_tbl_sz = msix_ctrl & 0x7ff; 334 ixgbe_log(ixgbe, 335 "PCI_MSIX_CTRL:\t0x%x\n", msix_ctrl); 336 337 tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET); 338 tbl_bir = tbl_offset & PCI_MSIX_TBL_BIR_MASK; 339 tbl_offset = tbl_offset & ~PCI_MSIX_TBL_BIR_MASK; 340 ixgbe_log(ixgbe, 341 "PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset); 342 ixgbe_log(ixgbe, 343 "PCI_MSIX_TBL_BIR:\t0x%x\n", tbl_bir); 344 345 pba_offset = pci_config_get32(handle, offset + PCI_MSIX_PBA_OFFSET); 346 pba_bir = pba_offset & PCI_MSIX_PBA_BIR_MASK; 347 pba_offset = pba_offset & ~PCI_MSIX_PBA_BIR_MASK; 348 ixgbe_log(ixgbe, 349 "PCI_MSIX_PBA_OFFSET:\t0x%x\n", pba_offset); 350 ixgbe_log(ixgbe, 351 "PCI_MSIX_PBA_BIR:\t0x%x\n", pba_bir); 352 353 /* PCI Express Configuration */ 354 offset = next_ptr; 355 356 ixgbe_log(ixgbe, 357 "PCIE_CAP_ID:\t0x%x\n", 358 pci_config_get8(handle, offset + PCIE_CAP_ID)); 359 360 next_ptr = pci_config_get8(handle, offset + PCIE_CAP_NEXT_PTR); 361 362 ixgbe_log(ixgbe, 363 "PCIE_CAP_NEXT_PTR:\t0x%x\n", next_ptr); 364 ixgbe_log(ixgbe, 365 "PCIE_PCIECAP:\t0x%x\n", 366 pci_config_get16(handle, offset + PCIE_PCIECAP)); 367 ixgbe_log(ixgbe, 368 "PCIE_DEVCAP:\t0x%x\n", 369 pci_config_get32(handle, offset + PCIE_DEVCAP)); 370 ixgbe_log(ixgbe, 371 "PCIE_DEVCTL:\t0x%x\n", 372 pci_config_get16(handle, offset + PCIE_DEVCTL)); 373 ixgbe_log(ixgbe, 374 "PCIE_DEVSTS:\t0x%x\n", 375 pci_config_get16(handle, offset + PCIE_DEVSTS)); 376 ixgbe_log(ixgbe, 377 "PCIE_LINKCAP:\t0x%x\n", 378 pci_config_get32(handle, offset + PCIE_LINKCAP)); 379 ixgbe_log(ixgbe, 380 "PCIE_LINKCTL:\t0x%x\n", 381 pci_config_get16(handle, offset + PCIE_LINKCTL)); 382 ixgbe_log(ixgbe, 383 "PCIE_LINKSTS:\t0x%x\n", 384 pci_config_get16(handle, offset + PCIE_LINKSTS)); 385 386 /* MSI-X Memory Space */ 387 if (ddi_dev_regsize(ixgbe->dip, 4, &mem_size) != DDI_SUCCESS) { 388 ixgbe_log(ixgbe, "ddi_dev_regsize() failed"); 389 return; 390 } 391 392 if ((ddi_regs_map_setup(ixgbe->dip, 4, (caddr_t *)&base, 0, mem_size, 393 &ixgbe_regs_acc_attr, &acc_hdl)) != DDI_SUCCESS) { 394 ixgbe_log(ixgbe, "ddi_regs_map_setup() failed"); 395 return; 396 } 397 398 ixgbe_log(ixgbe, "MSI-X Memory Space: (mem_size = %d, base = %x)", 399 mem_size, base); 400 401 for (i = 0; i <= msix_tbl_sz; i++) { 402 ixgbe_log(ixgbe, "MSI-X Table Entry(%d):", i); 403 ixgbe_log(ixgbe, "lo_addr:\t%x", 404 ddi_get32(acc_hdl, 405 (uint32_t *)(base + tbl_offset + (i * 16)))); 406 ixgbe_log(ixgbe, "up_addr:\t%x", 407 ddi_get32(acc_hdl, 408 (uint32_t *)(base + tbl_offset + (i * 16) + 4))); 409 ixgbe_log(ixgbe, "msg_data:\t%x", 410 ddi_get32(acc_hdl, 411 (uint32_t *)(base + tbl_offset + (i * 16) + 8))); 412 ixgbe_log(ixgbe, "vct_ctrl:\t%x", 413 ddi_get32(acc_hdl, 414 (uint32_t *)(base + tbl_offset + (i * 16) + 12))); 415 } 416 417 ixgbe_log(ixgbe, "MSI-X Pending Bits:\t%x", 418 ddi_get32(acc_hdl, (uint32_t *)(base + pba_offset))); 419 420 ddi_regs_map_free(&acc_hdl); 421 } 422 423 /* 424 * Dump registers 425 */ 426 void 427 ixgbe_dump_regs(void *adapter) 428 { 429 ixgbe_t *ixgbe = (ixgbe_t *)adapter; 430 uint32_t reg_val; 431 struct ixgbe_hw *hw = &ixgbe->hw; 432 int i; 433 DEBUGFUNC("ixgbe_dump_regs"); 434 435 /* Dump basic's like CTRL, STATUS, CTRL_EXT. */ 436 ixgbe_log(ixgbe, "Basic IXGBE registers.."); 437 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 438 ixgbe_log(ixgbe, "\tCTRL=%x\n", reg_val); 439 reg_val = IXGBE_READ_REG(hw, IXGBE_STATUS); 440 ixgbe_log(ixgbe, "\tSTATUS=%x\n", reg_val); 441 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 442 ixgbe_log(ixgbe, "\tCTRL_EXT=%x\n", reg_val); 443 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL); 444 ixgbe_log(ixgbe, "\tFCTRL=%x\n", reg_val); 445 446 /* Misc Interrupt regs */ 447 ixgbe_log(ixgbe, "Some IXGBE interrupt registers.."); 448 449 reg_val = IXGBE_READ_REG(hw, IXGBE_GPIE); 450 ixgbe_log(ixgbe, "\tGPIE=%x\n", reg_val); 451 452 reg_val = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 453 ixgbe_log(ixgbe, "\tIVAR(0)=%x\n", reg_val); 454 455 reg_val = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 456 ixgbe_log(ixgbe, "\tIVAR_MISC=%x\n", reg_val); 457 458 /* Dump RX related reg's */ 459 ixgbe_log(ixgbe, "Receive registers..."); 460 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 461 ixgbe_log(ixgbe, "\tRXCTRL=%x\n", reg_val); 462 for (i = 0; i < ixgbe->num_rx_rings; i++) { 463 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 464 ixgbe_log(ixgbe, "\tRXDCTL(%d)=%x\n", i, reg_val); 465 reg_val = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 466 ixgbe_log(ixgbe, "\tSRRCTL(%d)=%x\n", i, reg_val); 467 } 468 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 469 ixgbe_log(ixgbe, "\tRXCSUM=%x\n", reg_val); 470 reg_val = IXGBE_READ_REG(hw, IXGBE_MRQC); 471 ixgbe_log(ixgbe, "\tMRQC=%x\n", reg_val); 472 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 473 ixgbe_log(ixgbe, "\tRDRXCTL=%x\n", reg_val); 474 475 /* Dump TX related regs */ 476 ixgbe_log(ixgbe, "Some transmit registers.."); 477 reg_val = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 478 ixgbe_log(ixgbe, "\tDMATXCTL=%x\n", reg_val); 479 for (i = 0; i < ixgbe->num_tx_rings; i++) { 480 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 481 ixgbe_log(ixgbe, "\tTXDCTL(%d)=%x\n", i, reg_val); 482 reg_val = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 483 ixgbe_log(ixgbe, "\tTDWBAL(%d)=%x\n", i, reg_val); 484 reg_val = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 485 ixgbe_log(ixgbe, "\tTDWBAH(%d)=%x\n", i, reg_val); 486 reg_val = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 487 ixgbe_log(ixgbe, "\tTXPBSIZE(%d)=%x\n", i, reg_val); 488 } 489 } 490 491 #endif 492
Indexes created Mon Nov 23 13:58:57 UTC 2009
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