1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 /* IntelVersion: 1.98 scm_100309_002210 */ 30 31 #include "ixgbe_api.h" 32 #include "ixgbe_common.h" 33 #include "ixgbe_phy.h" 34 35 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 45 static bool ixgbe_get_i2c_data(u32 *i2cctl); 46 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 47 48 /* 49 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 50 * @hw: pointer to the hardware structure 51 * 52 * Initialize the function pointers. 53 */ 54 s32 55 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 56 { 57 struct ixgbe_phy_info *phy = &hw->phy; 58 59 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 60 61 /* PHY */ 62 phy->ops.identify = &ixgbe_identify_phy_generic; 63 phy->ops.reset = &ixgbe_reset_phy_generic; 64 phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 65 phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 66 phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 67 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 68 phy->ops.check_link = NULL; 69 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 70 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 71 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 72 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 73 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 74 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 75 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic; 76 phy->sfp_type = ixgbe_sfp_type_unknown; 77 78 return (IXGBE_SUCCESS); 79 } 80 81 /* 82 * ixgbe_identify_phy_generic - Get physical layer module 83 * @hw: pointer to hardware structure 84 * 85 * Determines the physical layer module found on the current adapter. 86 */ 87 s32 88 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 89 { 90 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 91 u32 phy_addr; 92 u16 ext_ability = 0; 93 94 DEBUGFUNC("ixgbe_identify_phy_generic"); 95 96 if (hw->phy.type == ixgbe_phy_unknown) { 97 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 98 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 99 hw->phy.addr = phy_addr; 100 (void) ixgbe_get_phy_id(hw); 101 hw->phy.type = 102 ixgbe_get_phy_type_from_id(hw->phy.id); 103 104 if (hw->phy.type == ixgbe_phy_unknown) { 105 hw->phy.ops.read_reg(hw, 106 IXGBE_MDIO_PHY_EXT_ABILITY, 107 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 108 &ext_ability); 109 if (ext_ability & 110 IXGBE_MDIO_PHY_10GBASET_ABILITY || 111 ext_ability & 112 IXGBE_MDIO_PHY_1000BASET_ABILITY) 113 hw->phy.type = 114 ixgbe_phy_cu_unknown; 115 else 116 hw->phy.type = 117 ixgbe_phy_generic; 118 } 119 120 status = IXGBE_SUCCESS; 121 break; 122 } 123 } 124 if (status != IXGBE_SUCCESS) 125 hw->phy.addr = 0; 126 } else { 127 status = IXGBE_SUCCESS; 128 } 129 130 return (status); 131 } 132 133 /* 134 * ixgbe_validate_phy_addr - Determines phy address is valid 135 * @hw: pointer to hardware structure 136 * 137 */ 138 bool 139 ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 140 { 141 u16 phy_id = 0; 142 bool valid = false; 143 144 DEBUGFUNC("ixgbe_validate_phy_addr"); 145 146 hw->phy.addr = phy_addr; 147 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 148 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 149 150 if (phy_id != 0xFFFF && phy_id != 0x0) 151 valid = true; 152 153 return (valid); 154 } 155 156 /* 157 * ixgbe_get_phy_id - Get the phy type 158 * @hw: pointer to hardware structure 159 * 160 */ 161 s32 162 ixgbe_get_phy_id(struct ixgbe_hw *hw) 163 { 164 u32 status; 165 u16 phy_id_high = 0; 166 u16 phy_id_low = 0; 167 168 DEBUGFUNC("ixgbe_get_phy_id"); 169 170 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 171 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 172 &phy_id_high); 173 174 if (status == IXGBE_SUCCESS) { 175 hw->phy.id = (u32)(phy_id_high << 16); 176 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 177 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 178 &phy_id_low); 179 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 180 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 181 } 182 183 return (status); 184 } 185 186 /* 187 * ixgbe_get_phy_type_from_id - Get the phy type 188 * @hw: pointer to hardware structure 189 * 190 */ 191 enum ixgbe_phy_type 192 ixgbe_get_phy_type_from_id(u32 phy_id) 193 { 194 enum ixgbe_phy_type phy_type; 195 196 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 197 198 switch (phy_id) { 199 case TN1010_PHY_ID: 200 phy_type = ixgbe_phy_tn; 201 break; 202 case AQ1002_PHY_ID: 203 phy_type = ixgbe_phy_aq; 204 break; 205 case QT2022_PHY_ID: 206 phy_type = ixgbe_phy_qt; 207 break; 208 case ATH_PHY_ID: 209 phy_type = ixgbe_phy_nl; 210 break; 211 default: 212 phy_type = ixgbe_phy_unknown; 213 break; 214 } 215 216 DEBUGOUT1("phy type found is %d\n", phy_type); 217 218 return (phy_type); 219 } 220 221 /* 222 * ixgbe_reset_phy_generic - Performs a PHY reset 223 * @hw: pointer to hardware structure 224 */ 225 s32 226 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 227 { 228 u32 i; 229 u16 ctrl = 0; 230 s32 status = IXGBE_SUCCESS; 231 232 DEBUGFUNC("ixgbe_reset_phy_generic"); 233 234 if (hw->phy.type == ixgbe_phy_unknown) 235 status = ixgbe_identify_phy_generic(hw); 236 237 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 238 goto out; 239 240 /* 241 * Perform soft PHY reset to the PHY_XS. 242 * This will cause a soft reset to the PHY 243 */ 244 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 245 IXGBE_MDIO_PHY_XS_DEV_TYPE, 246 IXGBE_MDIO_PHY_XS_RESET); 247 248 /* Poll for reset bit to self-clear indicating reset is complete */ 249 for (i = 0; i < 500; i++) { 250 msec_delay(1); 251 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 252 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 253 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) 254 break; 255 } 256 257 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 258 status = IXGBE_ERR_RESET_FAILED; 259 DEBUGOUT("PHY reset polling failed to complete.\n"); 260 } 261 262 out: 263 return (status); 264 } 265 266 /* 267 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 268 * @hw: pointer to hardware structure 269 * @reg_addr: 32 bit address of PHY register to read 270 * @phy_data: Pointer to read data from PHY register 271 */ 272 s32 273 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 274 u32 device_type, u16 *phy_data) 275 { 276 u32 command; 277 u32 i; 278 u32 data; 279 s32 status = IXGBE_SUCCESS; 280 u16 gssr; 281 282 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 283 284 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 285 gssr = IXGBE_GSSR_PHY1_SM; 286 else 287 gssr = IXGBE_GSSR_PHY0_SM; 288 289 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 290 status = IXGBE_ERR_SWFW_SYNC; 291 292 if (status == IXGBE_SUCCESS) { 293 /* Setup and write the address cycle command */ 294 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 295 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 296 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 297 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 298 299 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 300 301 /* 302 * Check every 10 usec to see if the address cycle completed. 303 * The MDI Command bit will clear when the operation is 304 * complete 305 */ 306 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 307 usec_delay(10); 308 309 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 310 311 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) { 312 break; 313 } 314 } 315 316 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 317 DEBUGOUT("PHY address command did not complete.\n"); 318 status = IXGBE_ERR_PHY; 319 } 320 321 if (status == IXGBE_SUCCESS) { 322 /* 323 * Address cycle complete, setup and write the read 324 * command 325 */ 326 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 327 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 328 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 329 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 330 331 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 332 333 /* 334 * Check every 10 usec to see if the address cycle 335 * completed. The MDI Command bit will clear when the 336 * operation is complete 337 */ 338 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 339 usec_delay(10); 340 341 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 342 343 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 344 break; 345 } 346 347 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 348 DEBUGOUT("PHY read command didn't complete\n"); 349 status = IXGBE_ERR_PHY; 350 } else { 351 /* 352 * Read operation is complete. Get the data 353 * from MSRWD 354 */ 355 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 356 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 357 *phy_data = (u16)(data); 358 } 359 } 360 361 ixgbe_release_swfw_sync(hw, gssr); 362 } 363 364 return (status); 365 } 366 367 /* 368 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 369 * @hw: pointer to hardware structure 370 * @reg_addr: 32 bit PHY register to write 371 * @device_type: 5 bit device type 372 * @phy_data: Data to write to the PHY register 373 */ 374 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 375 u32 device_type, u16 phy_data) 376 { 377 u32 command; 378 u32 i; 379 s32 status = IXGBE_SUCCESS; 380 u16 gssr; 381 382 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 383 384 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 385 gssr = IXGBE_GSSR_PHY1_SM; 386 else 387 gssr = IXGBE_GSSR_PHY0_SM; 388 389 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 390 status = IXGBE_ERR_SWFW_SYNC; 391 392 if (status == IXGBE_SUCCESS) { 393 /* 394 * Put the data in the MDI single read and write data register 395 */ 396 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 397 398 /* Setup and write the address cycle command */ 399 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 400 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 401 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 402 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 403 404 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 405 406 /* 407 * Check every 10 usec to see if the address cycle completed. 408 * The MDI Command bit will clear when the operation is 409 * complete 410 */ 411 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 412 usec_delay(10); 413 414 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 415 416 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 417 break; 418 } 419 420 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 421 DEBUGOUT("PHY address cmd didn't complete\n"); 422 status = IXGBE_ERR_PHY; 423 } 424 425 if (status == IXGBE_SUCCESS) { 426 /* 427 * Address cycle complete, setup and write the write 428 * command 429 */ 430 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 431 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 432 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 433 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 434 435 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 436 437 /* 438 * Check every 10 usec to see if the address cycle 439 * completed. The MDI Command bit will clear when the 440 * operation is complete 441 */ 442 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 443 usec_delay(10); 444 445 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 446 447 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 448 break; 449 } 450 451 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 452 DEBUGOUT("PHY address cmd didn't complete\n"); 453 status = IXGBE_ERR_PHY; 454 } 455 } 456 457 ixgbe_release_swfw_sync(hw, gssr); 458 } 459 460 return (status); 461 } 462 463 /* 464 * ixgbe_setup_phy_link_generic - Set and restart autoneg 465 * @hw: pointer to hardware structure 466 * 467 * Restart autonegotiation and PHY and waits for completion. 468 */ 469 s32 470 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 471 { 472 s32 status = IXGBE_SUCCESS; 473 u32 time_out; 474 u32 max_time_out = 10; 475 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 476 bool autoneg = false; 477 ixgbe_link_speed speed; 478 479 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 480 481 (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 482 483 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 484 /* Set or unset auto-negotiation 10G advertisement */ 485 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 486 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 487 &autoneg_reg); 488 489 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 490 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 491 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 492 493 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 494 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 495 autoneg_reg); 496 } 497 498 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 499 /* Set or unset auto-negotiation 1G advertisement */ 500 hw->phy.ops.read_reg(hw, 501 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 502 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 503 &autoneg_reg); 504 505 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 506 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 507 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 508 509 hw->phy.ops.write_reg(hw, 510 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 511 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 512 autoneg_reg); 513 } 514 515 if (speed & IXGBE_LINK_SPEED_100_FULL) { 516 /* Set or unset auto-negotiation 100M advertisement */ 517 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 518 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 519 &autoneg_reg); 520 521 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 522 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 523 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 524 525 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 526 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 527 autoneg_reg); 528 } 529 530 /* Restart PHY autonegotiation and wait for completion */ 531 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 532 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 533 534 autoneg_reg |= IXGBE_MII_RESTART; 535 536 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 537 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 538 539 /* Wait for autonegotiation to finish */ 540 for (time_out = 0; time_out < max_time_out; time_out++) { 541 usec_delay(10); 542 /* Restart PHY autonegotiation and wait for completion */ 543 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 544 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 545 &autoneg_reg); 546 547 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 548 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 549 break; 550 } 551 } 552 553 if (time_out == max_time_out) { 554 status = IXGBE_ERR_LINK_SETUP; 555 DEBUGOUT("ixgbe_setup_phy_link_generic: time out"); 556 } 557 558 return (status); 559 } 560 561 /* 562 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 563 * @hw: pointer to hardware structure 564 * @speed: new link speed 565 * @autoneg: true if autonegotiation enabled 566 */ 567 s32 568 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 569 ixgbe_link_speed speed, 570 bool autoneg, 571 bool autoneg_wait_to_complete) 572 { 573 UNREFERENCED_PARAMETER(autoneg); 574 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 575 576 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 577 578 /* 579 * Clear autoneg_advertised and set new values based on input link 580 * speed. 581 */ 582 hw->phy.autoneg_advertised = 0; 583 584 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 585 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 586 } 587 588 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 589 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 590 } 591 592 if (speed & IXGBE_LINK_SPEED_100_FULL) 593 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 594 595 /* Setup link based on the new speed settings */ 596 hw->phy.ops.setup_link(hw); 597 598 return (IXGBE_SUCCESS); 599 } 600 601 /* 602 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 603 * @hw: pointer to hardware structure 604 * @speed: pointer to link speed 605 * @autoneg: boolean auto-negotiation value 606 * 607 * Determines the link capabilities by reading the AUTOC register. 608 */ 609 s32 610 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 611 ixgbe_link_speed *speed, bool *autoneg) 612 { 613 s32 status = IXGBE_ERR_LINK_SETUP; 614 u16 speed_ability; 615 616 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 617 618 *speed = 0; 619 *autoneg = true; 620 621 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 622 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &speed_ability); 623 624 if (status == IXGBE_SUCCESS) { 625 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 626 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 628 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 629 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 630 *speed |= IXGBE_LINK_SPEED_100_FULL; 631 } 632 633 return (status); 634 } 635 636 /* 637 * ixgbe_check_phy_link_tnx - Determine link and speed status 638 * @hw: pointer to hardware structure 639 * 640 * Reads the VS1 register to determine if link is up and the current speed for 641 * the PHY. 642 */ 643 s32 644 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 645 bool *link_up) 646 { 647 s32 status = IXGBE_SUCCESS; 648 u32 time_out; 649 u32 max_time_out = 10; 650 u16 phy_link = 0; 651 u16 phy_speed = 0; 652 u16 phy_data = 0; 653 654 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 655 656 /* Initialize speed and link to default case */ 657 *link_up = false; 658 *speed = IXGBE_LINK_SPEED_10GB_FULL; 659 660 /* 661 * Check current speed and link status of the PHY register. 662 * This is a vendor specific register and may have to 663 * be changed for other copper PHYs. 664 */ 665 for (time_out = 0; time_out < max_time_out; time_out++) { 666 usec_delay(10); 667 status = hw->phy.ops.read_reg(hw, 668 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 669 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 670 &phy_data); 671 phy_link = phy_data & 672 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 673 phy_speed = phy_data & 674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 675 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 676 *link_up = true; 677 if (phy_speed == 678 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 679 *speed = IXGBE_LINK_SPEED_1GB_FULL; 680 break; 681 } 682 } 683 684 return (status); 685 } 686 687 /* 688 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 689 * @hw: pointer to hardware structure 690 * 691 * Restart autonegotiation and PHY and waits for completion. 692 */ 693 s32 694 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 695 { 696 s32 status = IXGBE_SUCCESS; 697 u32 time_out; 698 u32 max_time_out = 10; 699 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 700 bool autoneg = false; 701 ixgbe_link_speed speed; 702 703 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 704 705 (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 706 707 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 708 /* Set or unset auto-negotiation 10G advertisement */ 709 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 710 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 711 &autoneg_reg); 712 713 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 714 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 715 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 716 717 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 718 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 719 autoneg_reg); 720 } 721 722 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 723 /* Set or unset auto-negotiation 1G advertisement */ 724 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 725 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 726 &autoneg_reg); 727 728 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 729 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 730 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 731 732 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 733 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 734 autoneg_reg); 735 } 736 737 if (speed & IXGBE_LINK_SPEED_100_FULL) { 738 /* Set or unset auto-negotiation 100M advertisement */ 739 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 740 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 741 &autoneg_reg); 742 743 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 744 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 745 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 746 747 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 748 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 749 autoneg_reg); 750 } 751 752 /* Restart PHY autonegotiation and wait for completion */ 753 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 754 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 755 756 autoneg_reg |= IXGBE_MII_RESTART; 757 758 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 760 761 /* Wait for autonegotiation to finish */ 762 for (time_out = 0; time_out < max_time_out; time_out++) { 763 usec_delay(10); 764 /* Restart PHY autonegotiation and wait for completion */ 765 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 766 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 767 &autoneg_reg); 768 769 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 770 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { 771 break; 772 } 773 } 774 775 if (time_out == max_time_out) { 776 status = IXGBE_ERR_LINK_SETUP; 777 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 778 } 779 780 return (status); 781 } 782 783 /* 784 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 785 * @hw: pointer to hardware structure 786 * @firmware_version: pointer to the PHY Firmware Version 787 */ 788 s32 789 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version) 790 { 791 s32 status = IXGBE_SUCCESS; 792 793 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 794 795 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 796 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 797 798 return (status); 799 } 800 801 /* 802 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 803 * @hw: pointer to hardware structure 804 * @firmware_version: pointer to the PHY Firmware Version 805 */ 806 s32 807 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 808 u16 *firmware_version) 809 { 810 s32 status = IXGBE_SUCCESS; 811 812 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 813 814 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 815 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version); 816 817 return (status); 818 } 819 820 /* 821 * ixgbe_reset_phy_nl - Performs a PHY reset 822 * @hw: pointer to hardware structure 823 */ 824 s32 825 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 826 { 827 u16 phy_offset, control, eword, edata, block_crc; 828 bool end_data = false; 829 u16 list_offset, data_offset; 830 u16 phy_data = 0; 831 s32 ret_val = IXGBE_SUCCESS; 832 u32 i; 833 834 DEBUGFUNC("ixgbe_reset_phy_nl"); 835 836 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 837 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 838 839 /* reset the PHY and poll for completion */ 840 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 841 IXGBE_MDIO_PHY_XS_DEV_TYPE, 842 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 843 844 for (i = 0; i < 100; i++) { 845 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 846 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 847 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 848 break; 849 msec_delay(10); 850 } 851 852 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 853 DEBUGOUT("PHY reset did not complete.\n"); 854 ret_val = IXGBE_ERR_PHY; 855 goto out; 856 } 857 858 /* Get init offsets */ 859 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 860 &data_offset); 861 if (ret_val != IXGBE_SUCCESS) 862 goto out; 863 864 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 865 data_offset++; 866 while (!end_data) { 867 /* 868 * Read control word from PHY init contents offset 869 */ 870 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 871 control = (eword & IXGBE_CONTROL_MASK_NL) >> 872 IXGBE_CONTROL_SHIFT_NL; 873 edata = eword & IXGBE_DATA_MASK_NL; 874 switch (control) { 875 case IXGBE_DELAY_NL: 876 data_offset++; 877 DEBUGOUT1("DELAY: %d MS\n", edata); 878 msec_delay(edata); 879 break; 880 case IXGBE_DATA_NL: 881 DEBUGOUT("DATA: \n"); 882 data_offset++; 883 hw->eeprom.ops.read(hw, data_offset++, &phy_offset); 884 for (i = 0; i < edata; i++) { 885 hw->eeprom.ops.read(hw, data_offset, &eword); 886 hw->phy.ops.write_reg(hw, phy_offset, 887 IXGBE_TWINAX_DEV, eword); 888 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 889 phy_offset); 890 data_offset++; 891 phy_offset++; 892 } 893 break; 894 case IXGBE_CONTROL_NL: 895 data_offset++; 896 DEBUGOUT("CONTROL: \n"); 897 if (edata == IXGBE_CONTROL_EOL_NL) { 898 DEBUGOUT("EOL\n"); 899 end_data = true; 900 } else if (edata == IXGBE_CONTROL_SOL_NL) { 901 DEBUGOUT("SOL\n"); 902 } else { 903 DEBUGOUT("Bad control value\n"); 904 ret_val = IXGBE_ERR_PHY; 905 goto out; 906 } 907 break; 908 default: 909 DEBUGOUT("Bad control type\n"); 910 ret_val = IXGBE_ERR_PHY; 911 goto out; 912 } 913 } 914 915 out: 916 return (ret_val); 917 } 918 919 /* 920 * ixgbe_identify_sfp_module_generic - Identifies SFP module 921 * @hw: pointer to hardware structure 922 * 923 * Searches for and identifies the SFP module and assigns appropriate PHY type. 924 */ 925 s32 926 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 927 { 928 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 929 u32 vendor_oui = 0; 930 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 931 u8 identifier = 0; 932 u8 comp_codes_1g = 0; 933 u8 comp_codes_10g = 0; 934 u8 oui_bytes[3] = {0, 0, 0}; 935 u8 cable_tech = 0; 936 u16 enforce_sfp = 0; 937 938 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 939 940 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 941 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 942 status = IXGBE_ERR_SFP_NOT_PRESENT; 943 goto out; 944 } 945 946 status = hw->phy.ops.read_i2c_eeprom(hw, 947 IXGBE_SFF_IDENTIFIER, &identifier); 948 949 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 950 status = IXGBE_ERR_SFP_NOT_PRESENT; 951 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 952 if (hw->phy.type != ixgbe_phy_nl) { 953 hw->phy.id = 0; 954 hw->phy.type = ixgbe_phy_unknown; 955 } 956 goto out; 957 } 958 959 /* LAN ID is needed for sfp_type determination */ 960 hw->mac.ops.set_lan_id(hw); 961 962 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 963 hw->phy.type = ixgbe_phy_sfp_unsupported; 964 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 965 } else { 966 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 967 &comp_codes_1g); 968 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 969 &comp_codes_10g); 970 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 971 &cable_tech); 972 973 /* 974 * ID Module 975 * ============ 976 * 0 SFP_DA_CU 977 * 1 SFP_SR 978 * 2 SFP_LR 979 * 3 SFP_DA_CORE0 - 82599-specific 980 * 4 SFP_DA_CORE1 - 82599-specific 981 * 5 SFP_SR/LR_CORE0 - 82599-specific 982 * 6 SFP_SR/LR_CORE1 - 82599-specific 983 */ 984 if (hw->mac.type == ixgbe_mac_82598EB) { 985 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 986 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 987 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 988 hw->phy.sfp_type = ixgbe_sfp_type_sr; 989 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 990 hw->phy.sfp_type = ixgbe_sfp_type_lr; 991 else 992 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 993 } else if (hw->mac.type == ixgbe_mac_82599EB) { 994 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 995 if (hw->bus.lan_id == 0) 996 hw->phy.sfp_type = 997 ixgbe_sfp_type_da_cu_core0; 998 else 999 hw->phy.sfp_type = 1000 ixgbe_sfp_type_da_cu_core1; 1001 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1002 if (hw->bus.lan_id == 0) 1003 hw->phy.sfp_type = 1004 ixgbe_sfp_type_srlr_core0; 1005 else 1006 hw->phy.sfp_type = 1007 ixgbe_sfp_type_srlr_core1; 1008 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1009 if (hw->bus.lan_id == 0) 1010 hw->phy.sfp_type = 1011 ixgbe_sfp_type_srlr_core0; 1012 else 1013 hw->phy.sfp_type = 1014 ixgbe_sfp_type_srlr_core1; 1015 else 1016 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1017 } 1018 1019 if (hw->phy.sfp_type != stored_sfp_type) 1020 hw->phy.sfp_setup_needed = true; 1021 1022 /* Determine if the SFP+ PHY is dual speed or not. */ 1023 hw->phy.multispeed_fiber = false; 1024 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1025 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1026 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1027 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1028 hw->phy.multispeed_fiber = true; 1029 1030 /* Determine PHY vendor */ 1031 if (hw->phy.type != ixgbe_phy_nl) { 1032 hw->phy.id = identifier; 1033 hw->phy.ops.read_i2c_eeprom(hw, 1034 IXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 1035 hw->phy.ops.read_i2c_eeprom(hw, 1036 IXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 1037 hw->phy.ops.read_i2c_eeprom(hw, 1038 IXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 1039 1040 vendor_oui = 1041 ((oui_bytes[0] << 1042 IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1043 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1044 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1045 1046 switch (vendor_oui) { 1047 case IXGBE_SFF_VENDOR_OUI_TYCO: 1048 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1049 hw->phy.type = ixgbe_phy_tw_tyco; 1050 break; 1051 case IXGBE_SFF_VENDOR_OUI_FTL: 1052 hw->phy.type = ixgbe_phy_sfp_ftl; 1053 break; 1054 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1055 hw->phy.type = ixgbe_phy_sfp_avago; 1056 break; 1057 case IXGBE_SFF_VENDOR_OUI_INTEL: 1058 hw->phy.type = ixgbe_phy_sfp_intel; 1059 break; 1060 default: 1061 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1062 hw->phy.type = ixgbe_phy_tw_unknown; 1063 else 1064 hw->phy.type = ixgbe_phy_sfp_unknown; 1065 break; 1066 } 1067 } 1068 1069 /* All passive DA cables are supported */ 1070 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1071 status = IXGBE_SUCCESS; 1072 goto out; 1073 } 1074 1075 /* 1G SFP modules are not supported */ 1076 if (comp_codes_10g == 0) { 1077 hw->phy.type = ixgbe_phy_sfp_unsupported; 1078 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1079 goto out; 1080 } 1081 1082 /* Anything else 82598-based is supported */ 1083 if (hw->mac.type == ixgbe_mac_82598EB) { 1084 status = IXGBE_SUCCESS; 1085 goto out; 1086 } 1087 1088 (void) ixgbe_get_device_caps(hw, &enforce_sfp); 1089 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1090 /* Make sure we're a supported PHY type */ 1091 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1092 status = IXGBE_SUCCESS; 1093 } else { 1094 DEBUGOUT("SFP+ module not supported\n"); 1095 hw->phy.type = ixgbe_phy_sfp_unsupported; 1096 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1097 } 1098 } else { 1099 status = IXGBE_SUCCESS; 1100 } 1101 } 1102 1103 out: 1104 return (status); 1105 } 1106 1107 1108 /* 1109 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1110 * @hw: pointer to hardware structure 1111 * @list_offset: offset to the SFP ID list 1112 * @data_offset: offset to the SFP data block 1113 * 1114 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1115 * so it returns the offsets to the phy init sequence block. 1116 */ 1117 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1118 u16 *list_offset, u16 *data_offset) 1119 { 1120 u16 sfp_id; 1121 1122 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1123 1124 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1125 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1126 1127 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1128 return (IXGBE_ERR_SFP_NOT_PRESENT); 1129 1130 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1131 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1132 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1133 1134 /* Read offset to PHY init contents */ 1135 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1136 1137 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1138 return (IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT); 1139 1140 /* Shift offset to first ID word */ 1141 (*list_offset)++; 1142 1143 /* 1144 * Find the matching SFP ID in the EEPROM 1145 * and program the init sequence 1146 */ 1147 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1148 1149 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1150 if (sfp_id == hw->phy.sfp_type) { 1151 (*list_offset)++; 1152 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1153 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1154 DEBUGOUT("SFP+ module not supported\n"); 1155 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1156 } else { 1157 break; 1158 } 1159 } else { 1160 (*list_offset) += 2; 1161 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1162 return (IXGBE_ERR_PHY); 1163 } 1164 } 1165 1166 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1167 DEBUGOUT("No matching SFP+ module found\n"); 1168 return (IXGBE_ERR_SFP_NOT_SUPPORTED); 1169 } 1170 1171 return (IXGBE_SUCCESS); 1172 } 1173 1174 /* 1175 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1176 * @hw: pointer to hardware structure 1177 * @byte_offset: EEPROM byte offset to read 1178 * @eeprom_data: value read 1179 * 1180 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1181 */ 1182 s32 1183 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1184 u8 *eeprom_data) 1185 { 1186 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1187 1188 return (hw->phy.ops.read_i2c_byte(hw, byte_offset, 1189 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 1190 } 1191 1192 /* 1193 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1194 * @hw: pointer to hardware structure 1195 * @byte_offset: EEPROM byte offset to write 1196 * @eeprom_data: value to write 1197 * 1198 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1199 */ 1200 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1201 u8 eeprom_data) 1202 { 1203 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1204 1205 return (hw->phy.ops.write_i2c_byte(hw, byte_offset, 1206 IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data)); 1207 } 1208 1209 /* 1210 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1211 * @hw: pointer to hardware structure 1212 * @byte_offset: byte offset to read 1213 * @data: value read 1214 * 1215 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1216 * a specified deivce address. 1217 */ 1218 s32 1219 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1220 u8 dev_addr, u8 *data) 1221 { 1222 s32 status = IXGBE_SUCCESS; 1223 u32 max_retry = 10; 1224 u32 retry = 0; 1225 u16 swfw_mask = 0; 1226 bool nack = 1; 1227 1228 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1229 1230 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1231 swfw_mask = IXGBE_GSSR_PHY1_SM; 1232 else 1233 swfw_mask = IXGBE_GSSR_PHY0_SM; 1234 1235 do { 1236 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1237 status = IXGBE_ERR_SWFW_SYNC; 1238 goto read_byte_out; 1239 } 1240 1241 ixgbe_i2c_start(hw); 1242 1243 /* Device Address and write indication */ 1244 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1245 if (status != IXGBE_SUCCESS) 1246 goto fail; 1247 1248 status = ixgbe_get_i2c_ack(hw); 1249 if (status != IXGBE_SUCCESS) 1250 goto fail; 1251 1252 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1253 if (status != IXGBE_SUCCESS) 1254 goto fail; 1255 1256 status = ixgbe_get_i2c_ack(hw); 1257 if (status != IXGBE_SUCCESS) 1258 goto fail; 1259 1260 ixgbe_i2c_start(hw); 1261 1262 /* Device Address and read indication */ 1263 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1264 if (status != IXGBE_SUCCESS) 1265 goto fail; 1266 1267 status = ixgbe_get_i2c_ack(hw); 1268 if (status != IXGBE_SUCCESS) 1269 goto fail; 1270 1271 status = ixgbe_clock_in_i2c_byte(hw, data); 1272 if (status != IXGBE_SUCCESS) 1273 goto fail; 1274 1275 status = ixgbe_clock_out_i2c_bit(hw, nack); 1276 if (status != IXGBE_SUCCESS) 1277 goto fail; 1278 1279 ixgbe_i2c_stop(hw); 1280 break; 1281 1282 fail: 1283 ixgbe_release_swfw_sync(hw, swfw_mask); 1284 msec_delay(100); 1285 ixgbe_i2c_bus_clear(hw); 1286 retry++; 1287 if (retry < max_retry) 1288 DEBUGOUT("I2C byte read error - Retrying.\n"); 1289 else 1290 DEBUGOUT("I2C byte read error.\n"); 1291 } while (retry < max_retry); 1292 1293 ixgbe_release_swfw_sync(hw, swfw_mask); 1294 1295 read_byte_out: 1296 return (status); 1297 } 1298 1299 /* 1300 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1301 * @hw: pointer to hardware structure 1302 * @byte_offset: byte offset to write 1303 * @data: value to write 1304 * 1305 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1306 * a specified device address. 1307 */ 1308 s32 1309 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1310 u8 dev_addr, u8 data) 1311 { 1312 s32 status = IXGBE_SUCCESS; 1313 u32 max_retry = 1; 1314 u32 retry = 0; 1315 u16 swfw_mask = 0; 1316 1317 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1318 1319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1320 swfw_mask = IXGBE_GSSR_PHY1_SM; 1321 else 1322 swfw_mask = IXGBE_GSSR_PHY0_SM; 1323 1324 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1325 status = IXGBE_ERR_SWFW_SYNC; 1326 goto write_byte_out; 1327 } 1328 1329 do { 1330 ixgbe_i2c_start(hw); 1331 1332 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1333 if (status != IXGBE_SUCCESS) 1334 goto fail; 1335 1336 status = ixgbe_get_i2c_ack(hw); 1337 if (status != IXGBE_SUCCESS) 1338 goto fail; 1339 1340 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1341 if (status != IXGBE_SUCCESS) 1342 goto fail; 1343 1344 status = ixgbe_get_i2c_ack(hw); 1345 if (status != IXGBE_SUCCESS) 1346 goto fail; 1347 1348 status = ixgbe_clock_out_i2c_byte(hw, data); 1349 if (status != IXGBE_SUCCESS) 1350 goto fail; 1351 1352 status = ixgbe_get_i2c_ack(hw); 1353 if (status != IXGBE_SUCCESS) 1354 goto fail; 1355 1356 ixgbe_i2c_stop(hw); 1357 break; 1358 1359 fail: 1360 ixgbe_i2c_bus_clear(hw); 1361 retry++; 1362 if (retry < max_retry) 1363 DEBUGOUT("I2C byte write error - Retrying.\n"); 1364 else 1365 DEBUGOUT("I2C byte write error.\n"); 1366 } while (retry < max_retry); 1367 1368 ixgbe_release_swfw_sync(hw, swfw_mask); 1369 1370 write_byte_out: 1371 return (status); 1372 } 1373 1374 /* 1375 * ixgbe_i2c_start - Sets I2C start condition 1376 * @hw: pointer to hardware structure 1377 * 1378 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1379 */ 1380 static void 1381 ixgbe_i2c_start(struct ixgbe_hw *hw) 1382 { 1383 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1384 1385 DEBUGFUNC("ixgbe_i2c_start"); 1386 1387 /* Start condition must begin with data and clock high */ 1388 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1389 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1390 1391 /* Setup time for start condition (4.7us) */ 1392 usec_delay(IXGBE_I2C_T_SU_STA); 1393 1394 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1395 1396 /* Hold time for start condition (4us) */ 1397 usec_delay(IXGBE_I2C_T_HD_STA); 1398 1399 ixgbe_lower_i2c_clk(hw, &i2cctl); 1400 1401 /* Minimum low period of clock is 4.7 us */ 1402 usec_delay(IXGBE_I2C_T_LOW); 1403 } 1404 1405 /* 1406 * ixgbe_i2c_stop - Sets I2C stop condition 1407 * @hw: pointer to hardware structure 1408 * 1409 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1410 */ 1411 static void 1412 ixgbe_i2c_stop(struct ixgbe_hw *hw) 1413 { 1414 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1415 1416 DEBUGFUNC("ixgbe_i2c_stop"); 1417 1418 /* Stop condition must begin with data low and clock high */ 1419 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0); 1420 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1421 1422 /* Setup time for stop condition (4us) */ 1423 usec_delay(IXGBE_I2C_T_SU_STO); 1424 1425 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1426 1427 /* bus free time between stop and start (4.7us) */ 1428 usec_delay(IXGBE_I2C_T_BUF); 1429 } 1430 1431 /* 1432 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1433 * @hw: pointer to hardware structure 1434 * @data: data byte to clock in 1435 * 1436 * Clocks in one byte data via I2C data/clock 1437 */ 1438 static s32 1439 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1440 { 1441 s32 status = IXGBE_SUCCESS; 1442 s32 i; 1443 bool bit = 0; 1444 1445 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1446 1447 for (i = 7; i >= 0; i--) { 1448 status = ixgbe_clock_in_i2c_bit(hw, &bit); 1449 *data |= bit<<i; 1450 1451 if (status != IXGBE_SUCCESS) 1452 break; 1453 } 1454 1455 return (status); 1456 } 1457 1458 /* 1459 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1460 * @hw: pointer to hardware structure 1461 * @data: data byte clocked out 1462 * 1463 * Clocks out one byte data via I2C data/clock 1464 */ 1465 static s32 1466 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1467 { 1468 s32 status = IXGBE_SUCCESS; 1469 s32 i; 1470 u32 i2cctl; 1471 bool bit = 0; 1472 1473 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1474 1475 for (i = 7; i >= 0; i--) { 1476 bit = (data >> i) & 0x1; 1477 status = ixgbe_clock_out_i2c_bit(hw, bit); 1478 1479 if (status != IXGBE_SUCCESS) 1480 break; 1481 } 1482 1483 /* Release SDA line (set high) */ 1484 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1485 i2cctl |= IXGBE_I2C_DATA_OUT; 1486 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1487 1488 return (status); 1489 } 1490 1491 /* 1492 * ixgbe_get_i2c_ack - Polls for I2C ACK 1493 * @hw: pointer to hardware structure 1494 * 1495 * Clocks in/out one bit via I2C data/clock 1496 */ 1497 static s32 1498 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1499 { 1500 s32 status; 1501 u32 i = 0; 1502 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1503 u32 timeout = 10; 1504 bool ack = 1; 1505 1506 DEBUGFUNC("ixgbe_get_i2c_ack"); 1507 1508 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1509 1510 if (status != IXGBE_SUCCESS) 1511 goto out; 1512 1513 /* Minimum high period of clock is 4us */ 1514 usec_delay(IXGBE_I2C_T_HIGH); 1515 1516 /* 1517 * Poll for ACK. Note that ACK in I2C spec is 1518 * transition from 1 to 0 1519 */ 1520 for (i = 0; i < timeout; i++) { 1521 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1522 ack = ixgbe_get_i2c_data(&i2cctl); 1523 1524 usec_delay(1); 1525 if (ack == 0) 1526 break; 1527 } 1528 1529 if (ack == 1) { 1530 DEBUGOUT("I2C ack was not received.\n"); 1531 status = IXGBE_ERR_I2C; 1532 } 1533 1534 ixgbe_lower_i2c_clk(hw, &i2cctl); 1535 1536 /* Minimum low period of clock is 4.7 us */ 1537 usec_delay(IXGBE_I2C_T_LOW); 1538 1539 out: 1540 return (status); 1541 } 1542 1543 /* 1544 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1545 * @hw: pointer to hardware structure 1546 * @data: read data value 1547 * 1548 * Clocks in one bit via I2C data/clock 1549 */ 1550 static s32 1551 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1552 { 1553 s32 status; 1554 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1555 1556 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1557 1558 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1559 1560 /* Minimum high period of clock is 4us */ 1561 usec_delay(IXGBE_I2C_T_HIGH); 1562 1563 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1564 *data = ixgbe_get_i2c_data(&i2cctl); 1565 1566 ixgbe_lower_i2c_clk(hw, &i2cctl); 1567 1568 /* Minimum low period of clock is 4.7 us */ 1569 usec_delay(IXGBE_I2C_T_LOW); 1570 1571 return (status); 1572 } 1573 1574 /* 1575 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1576 * @hw: pointer to hardware structure 1577 * @data: data value to write 1578 * 1579 * Clocks out one bit via I2C data/clock 1580 */ 1581 static s32 1582 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1583 { 1584 s32 status; 1585 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1586 1587 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1588 1589 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1590 if (status == IXGBE_SUCCESS) { 1591 status = ixgbe_raise_i2c_clk(hw, &i2cctl); 1592 1593 /* Minimum high period of clock is 4us */ 1594 usec_delay(IXGBE_I2C_T_HIGH); 1595 1596 ixgbe_lower_i2c_clk(hw, &i2cctl); 1597 1598 /* 1599 * Minimum low period of clock is 4.7 us. 1600 * This also takes care of the data hold time. 1601 */ 1602 usec_delay(IXGBE_I2C_T_LOW); 1603 } else { 1604 status = IXGBE_ERR_I2C; 1605 DEBUGOUT1("I2C data was not set to %X\n", data); 1606 } 1607 1608 return (status); 1609 } 1610 1611 /* 1612 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1613 * @hw: pointer to hardware structure 1614 * @i2cctl: Current value of I2CCTL register 1615 * 1616 * Raises the I2C clock line '0'->'1' 1617 */ 1618 static s32 1619 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1620 { 1621 s32 status = IXGBE_SUCCESS; 1622 1623 DEBUGFUNC("ixgbe_raise_i2c_clk"); 1624 1625 *i2cctl |= IXGBE_I2C_CLK_OUT; 1626 1627 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1628 1629 /* SCL rise time (1000ns) */ 1630 usec_delay(IXGBE_I2C_T_RISE); 1631 1632 return (status); 1633 } 1634 1635 /* 1636 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1637 * @hw: pointer to hardware structure 1638 * @i2cctl: Current value of I2CCTL register 1639 * 1640 * Lowers the I2C clock line '1'->'0' 1641 */ 1642 static void 1643 ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1644 { 1645 DEBUGFUNC("ixgbe_lower_i2c_clk"); 1646 1647 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1648 1649 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1650 1651 /* SCL fall time (300ns) */ 1652 usec_delay(IXGBE_I2C_T_FALL); 1653 } 1654 1655 /* 1656 * ixgbe_set_i2c_data - Sets the I2C data bit 1657 * @hw: pointer to hardware structure 1658 * @i2cctl: Current value of I2CCTL register 1659 * @data: I2C data value (0 or 1) to set 1660 * 1661 * Sets the I2C data bit 1662 */ 1663 static s32 1664 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1665 { 1666 s32 status = IXGBE_SUCCESS; 1667 1668 DEBUGFUNC("ixgbe_set_i2c_data"); 1669 1670 if (data) 1671 *i2cctl |= IXGBE_I2C_DATA_OUT; 1672 else 1673 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1674 1675 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1676 1677 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1678 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1679 1680 /* Verify data was set correctly */ 1681 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1682 if (data != ixgbe_get_i2c_data(i2cctl)) { 1683 status = IXGBE_ERR_I2C; 1684 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 1685 } 1686 1687 return (status); 1688 } 1689 1690 /* 1691 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1692 * @hw: pointer to hardware structure 1693 * @i2cctl: Current value of I2CCTL register 1694 * 1695 * Returns the I2C data bit value 1696 */ 1697 static bool 1698 ixgbe_get_i2c_data(u32 *i2cctl) 1699 { 1700 bool data; 1701 1702 DEBUGFUNC("ixgbe_get_i2c_data"); 1703 1704 if (*i2cctl & IXGBE_I2C_DATA_IN) 1705 data = 1; 1706 else 1707 data = 0; 1708 1709 return (data); 1710 } 1711 1712 /* 1713 * ixgbe_i2c_bus_clear - Clears the I2C bus 1714 * @hw: pointer to hardware structure 1715 * 1716 * Clears the I2C bus by sending nine clock pulses. 1717 * Used when data line is stuck low. 1718 */ 1719 void 1720 ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1721 { 1722 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1723 u32 i; 1724 1725 DEBUGFUNC("ixgbe_i2c_bus_clear"); 1726 1727 ixgbe_i2c_start(hw); 1728 1729 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1); 1730 1731 for (i = 0; i < 9; i++) { 1732 (void) ixgbe_raise_i2c_clk(hw, &i2cctl); 1733 1734 /* Min high period of clock is 4us */ 1735 usec_delay(IXGBE_I2C_T_HIGH); 1736 1737 ixgbe_lower_i2c_clk(hw, &i2cctl); 1738 1739 /* Min low period of clock is 4.7us */ 1740 usec_delay(IXGBE_I2C_T_LOW); 1741 } 1742 1743 ixgbe_i2c_start(hw); 1744 1745 /* Put the i2c bus back to default state */ 1746 ixgbe_i2c_stop(hw); 1747 } 1748
Indexes created Mon Nov 23 23:09:39 UTC 2009
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