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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
      5  * The contents of this file are subject to the terms of the
      6  * Common Development and Distribution License (the "License").
      7  * You may not use this file except in compliance with the License.
      8  *
      9  * You can obtain a copy of the license at:
     10  *      http://www.opensolaris.org/os/licensing.
     11  * See the License for the specific language governing permissions
     12  * and limitations under the License.
     13  *
     14  * When using or redistributing this file, you may do so under the
     15  * License only. No other modification of this header is permitted.
     16  *
     17  * If applicable, add the following below this CDDL HEADER, with the
     18  * fields enclosed by brackets "[]" replaced with your own identifying
     19  * information: Portions Copyright [yyyy] [name of copyright owner]
     20  *
     21  * CDDL HEADER END
     22  */
     23 
     24 /*
     25  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
     26  * Use is subject to license terms.
     27  */
     28 
     29 /* IntelVersion: 1.36 scm_100309_002210 */
     30 
     31 #ifndef _IXGBE_PHY_H
     32 #define	_IXGBE_PHY_H
     33 
     34 #include "ixgbe_type.h"
     35 
     36 #define	IXGBE_I2C_EEPROM_DEV_ADDR	0xA0
     37 
     38 /* EEPROM byte offsets */
     39 #define	IXGBE_SFF_IDENTIFIER		0x0
     40 #define	IXGBE_SFF_IDENTIFIER_SFP	0x3
     41 #define	IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
     42 #define	IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
     43 #define	IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
     44 #define	IXGBE_SFF_1GBE_COMP_CODES	0x6
     45 #define	IXGBE_SFF_10GBE_COMP_CODES	0x3
     46 #define	IXGBE_SFF_CABLE_TECHNOLOGY	0x8
     47 
     48 /* Bitmasks */
     49 #define	IXGBE_SFF_DA_PASSIVE_CABLE	0x4
     50 #define	IXGBE_SFF_1GBASESX_CAPABLE	0x1
     51 #define	IXGBE_SFF_1GBASELX_CAPABLE	0x2
     52 #define	IXGBE_SFF_10GBASESR_CAPABLE	0x10
     53 #define	IXGBE_SFF_10GBASELR_CAPABLE	0x20
     54 #define	IXGBE_I2C_EEPROM_READ_MASK	0x100
     55 #define	IXGBE_I2C_EEPROM_STATUS_MASK	0x3
     56 #define	IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
     57 #define	IXGBE_I2C_EEPROM_STATUS_PASS	0x1
     58 #define	IXGBE_I2C_EEPROM_STATUS_FAIL	0x2
     59 #define	IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
     60 
     61 /* Bit-shift macros */
     62 #define	IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT	24
     63 #define	IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT	16
     64 #define	IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT	8
     65 
     66 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
     67 #define	IXGBE_SFF_VENDOR_OUI_TYCO	0x00407600
     68 #define	IXGBE_SFF_VENDOR_OUI_FTL	0x00906500
     69 #define	IXGBE_SFF_VENDOR_OUI_AVAGO	0x00176A00
     70 #define	IXGBE_SFF_VENDOR_OUI_INTEL	0x001B2100
     71 
     72 /* I2C SDA and SCL timing parameters for standard mode */
     73 #define	IXGBE_I2C_T_HD_STA	4
     74 #define	IXGBE_I2C_T_LOW		5
     75 #define	IXGBE_I2C_T_HIGH	4
     76 #define	IXGBE_I2C_T_SU_STA	5
     77 #define	IXGBE_I2C_T_HD_DATA	5
     78 #define	IXGBE_I2C_T_SU_DATA	1
     79 #define	IXGBE_I2C_T_RISE	1
     80 #define	IXGBE_I2C_T_FALL	1
     81 #define	IXGBE_I2C_T_SU_STO	4
     82 #define	IXGBE_I2C_T_BUF		5
     83 
     84 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
     85 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
     86 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
     87 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
     88 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
     89 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
     90 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
     91     u32 device_type, u16 *phy_data);
     92 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
     93     u32 device_type, u16 phy_data);
     94 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
     95 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
     96     ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
     97 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
     98     ixgbe_link_speed *speed, bool *autoneg);
     99 
    100 /* PHY specific */
    101 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
    102     ixgbe_link_speed *speed, bool *link_up);
    103 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
    104 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
    105     u16 *firmware_version);
    106 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
    107     u16 *firmware_version);
    108 
    109 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
    110 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
    111 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
    112     u16 *list_offset, u16 *data_offset);
    113 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
    114     u8 dev_addr, u8 *data);
    115 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
    116     u8 dev_addr, u8 data);
    117 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
    118     u8 *eeprom_data);
    119 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
    120     u8 eeprom_data);
    121 
    122 #endif /* _IXGBE_PHY_H */
    123