1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IXGBE_SW_H 29 #define _IXGBE_SW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac_provider.h> 49 #include <sys/mac_ether.h> 50 #include <sys/vlan.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/pci.h> 54 #include <sys/pcie.h> 55 #include <sys/sdt.h> 56 #include <sys/ethernet.h> 57 #include <sys/pattr.h> 58 #include <sys/strsubr.h> 59 #include <sys/netlb.h> 60 #include <sys/random.h> 61 #include <inet/common.h> 62 #include <inet/tcp.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/bitmap.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "ixgbe_api.h" 72 73 #define MODULE_NAME "ixgbe" /* module name */ 74 75 #define IXGBE_FAILURE DDI_FAILURE 76 77 #define IXGBE_UNKNOWN 0x00 78 #define IXGBE_INITIALIZED 0x01 79 #define IXGBE_STARTED 0x02 80 #define IXGBE_SUSPENDED 0x04 81 82 #define MAX_NUM_UNICAST_ADDRESSES 0x10 83 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 84 #define IXGBE_INTR_NONE 0 85 #define IXGBE_INTR_MSIX 1 86 #define IXGBE_INTR_MSI 2 87 #define IXGBE_INTR_LEGACY 3 88 89 #define IXGBE_POLL_NULL -1 90 91 #define MAX_COOKIE 18 92 #define MIN_NUM_TX_DESC 2 93 94 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 95 96 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 97 98 #define IXGBE_RX_STOPPED 0x1 99 100 /* 101 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 102 * supported silicon types. 103 */ 104 #define MAX_TX_QUEUE_NUM 128 105 #define MAX_RX_QUEUE_NUM 128 106 #define MAX_INTR_VECTOR 64 107 108 /* 109 * Maximum values for user configurable parameters 110 */ 111 #define MAX_RX_GROUP_NUM 1 112 #define MAX_TX_RING_SIZE 4096 113 #define MAX_RX_RING_SIZE 4096 114 115 #define MAX_RX_LIMIT_PER_INTR 4096 116 117 #define MAX_RX_COPY_THRESHOLD 9216 118 #define MAX_TX_COPY_THRESHOLD 9216 119 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 120 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 121 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 122 123 /* 124 * Minimum values for user configurable parameters 125 */ 126 #define MIN_RX_GROUP_NUM 1 127 #define MIN_TX_RING_SIZE 64 128 #define MIN_RX_RING_SIZE 64 129 130 #define MIN_MTU ETHERMIN 131 #define MIN_RX_LIMIT_PER_INTR 16 132 #define MIN_TX_COPY_THRESHOLD 0 133 #define MIN_RX_COPY_THRESHOLD 0 134 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 135 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 136 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 137 138 /* 139 * Default values for user configurable parameters 140 */ 141 #define DEFAULT_RX_GROUP_NUM 1 142 #define DEFAULT_TX_RING_SIZE 1024 143 #define DEFAULT_RX_RING_SIZE 1024 144 145 #define DEFAULT_MTU ETHERMTU 146 #define DEFAULT_RX_LIMIT_PER_INTR 256 147 #define DEFAULT_RX_COPY_THRESHOLD 128 148 #define DEFAULT_TX_COPY_THRESHOLD 512 149 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 150 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 151 #define DEFAULT_TX_RESCHED_THRESHOLD 128 152 #define DEFAULT_FCRTH 0x20000 153 #define DEFAULT_FCRTL 0x10000 154 #define DEFAULT_FCPAUSE 0xFFFF 155 156 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 157 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 158 #define DEFAULT_LSO_ENABLE B_TRUE 159 #define DEFAULT_MR_ENABLE B_TRUE 160 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 161 162 #define IXGBE_LSO_MAXLEN 65535 163 164 #define TX_DRAIN_TIME 200 165 #define RX_DRAIN_TIME 200 166 167 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 168 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 169 170 /* 171 * Extra register bit masks for 82598 172 */ 173 #define IXGBE_PCS1GANA_FDC 0x20 174 #define IXGBE_PCS1GANLP_LPFD 0x20 175 #define IXGBE_PCS1GANLP_LPHD 0x40 176 177 /* 178 * Defined for IP header alignment. 179 */ 180 #define IPHDR_ALIGN_ROOM 2 181 182 /* 183 * Bit flags for attach_progress 184 */ 185 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 186 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 187 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 188 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 189 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 190 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 191 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 192 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 193 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 194 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 195 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 196 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 197 #define ATTACH_PROGRESS_LSC_TASKQ 0x4000 /* LSC taskq created */ 198 199 #define PROP_DEFAULT_MTU "default_mtu" 200 #define PROP_FLOW_CONTROL "flow_control" 201 #define PROP_TX_QUEUE_NUM "tx_queue_number" 202 #define PROP_TX_RING_SIZE "tx_ring_size" 203 #define PROP_RX_QUEUE_NUM "rx_queue_number" 204 #define PROP_RX_RING_SIZE "rx_ring_size" 205 #define PROP_RX_GROUP_NUM "rx_group_number" 206 207 #define PROP_INTR_FORCE "intr_force" 208 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 209 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 210 #define PROP_LSO_ENABLE "lso_enable" 211 #define PROP_MR_ENABLE "mr_enable" 212 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 213 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 214 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 215 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 216 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 217 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 218 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 219 #define PROP_INTR_THROTTLING "intr_throttling" 220 #define PROP_FM_CAPABLE "fm_capable" 221 222 #define IXGBE_LB_NONE 0 223 #define IXGBE_LB_EXTERNAL 1 224 #define IXGBE_LB_INTERNAL_MAC 2 225 #define IXGBE_LB_INTERNAL_PHY 3 226 #define IXGBE_LB_INTERNAL_SERDES 4 227 228 /* 229 * capability/feature flags 230 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 231 * Separately, the flag named _ENABLED is set when the feature is enabled. 232 */ 233 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 234 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 235 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 236 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 237 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 238 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 239 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 240 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 241 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 242 243 /* adapter-specific info for each supported device type */ 244 typedef struct adapter_info { 245 uint32_t max_rx_que_num; /* maximum number of rx queues */ 246 uint32_t min_rx_que_num; /* minimum number of rx queues */ 247 uint32_t def_rx_que_num; /* default number of rx queues */ 248 uint32_t max_tx_que_num; /* maximum number of tx queues */ 249 uint32_t min_tx_que_num; /* minimum number of tx queues */ 250 uint32_t def_tx_que_num; /* default number of tx queues */ 251 uint32_t max_mtu; /* maximum MTU size */ 252 /* 253 * Interrupt throttling is in unit of 256 nsec 254 */ 255 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 256 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 257 uint32_t def_intr_throttle; /* default interrupt throttle */ 258 259 uint32_t max_msix_vect; /* maximum total msix vectors */ 260 uint32_t max_ring_vect; /* maximum number of ring vectors */ 261 uint32_t max_other_vect; /* maximum number of other vectors */ 262 uint32_t other_intr; /* "other" interrupt types handled */ 263 uint32_t flags; /* capability flags */ 264 } adapter_info_t; 265 266 /* bits representing all interrupt types other than tx & rx */ 267 #define IXGBE_OTHER_INTR 0x3ff00000 268 #define IXGBE_82599_OTHER_INTR 0x86100000 269 270 enum ioc_reply { 271 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 272 IOC_DONE, /* OK, reply sent */ 273 IOC_ACK, /* OK, just send ACK */ 274 IOC_REPLY /* OK, just send reply */ 275 }; 276 277 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 278 0, 0, (flag))) 279 280 /* 281 * Defined for ring index operations 282 * ASSERT(index < limit) 283 * ASSERT(step < limit) 284 * ASSERT(index1 < limit) 285 * ASSERT(index2 < limit) 286 */ 287 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 288 (index) + (step) : (index) + (step) - (limit)) 289 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 290 (index) - (step) : (index) + (limit) - (step)) 291 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 292 (index2) - (index1) : (index2) + (limit) - (index1)) 293 294 #define LINK_LIST_INIT(_LH) \ 295 (_LH)->head = (_LH)->tail = NULL 296 297 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 298 299 #define LIST_POP_HEAD(_LH) \ 300 (single_link_t *)(_LH)->head; \ 301 { \ 302 if ((_LH)->head != NULL) { \ 303 (_LH)->head = (_LH)->head->link; \ 304 if ((_LH)->head == NULL) \ 305 (_LH)->tail = NULL; \ 306 } \ 307 } 308 309 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 310 311 #define LIST_PUSH_TAIL(_LH, _E) \ 312 if ((_LH)->tail != NULL) { \ 313 (_LH)->tail->link = (single_link_t *)(_E); \ 314 (_LH)->tail = (single_link_t *)(_E); \ 315 } else { \ 316 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 317 } \ 318 (_E)->link = NULL; 319 320 #define LIST_GET_NEXT(_LH, _E) \ 321 (((_LH)->tail == (single_link_t *)(_E)) ? \ 322 NULL : ((single_link_t *)(_E))->link) 323 324 325 typedef struct single_link { 326 struct single_link *link; 327 } single_link_t; 328 329 typedef struct link_list { 330 single_link_t *head; 331 single_link_t *tail; 332 } link_list_t; 333 334 /* 335 * Property lookups 336 */ 337 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 338 DDI_PROP_DONTPASS, (n)) 339 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 340 DDI_PROP_DONTPASS, (n), -1) 341 342 343 typedef union ixgbe_ether_addr { 344 struct { 345 uint32_t high; 346 uint32_t low; 347 } reg; 348 struct { 349 uint8_t set; 350 uint8_t redundant; 351 uint8_t addr[ETHERADDRL]; 352 } mac; 353 } ixgbe_ether_addr_t; 354 355 typedef enum { 356 USE_NONE, 357 USE_COPY, 358 USE_DMA 359 } tx_type_t; 360 361 typedef struct ixgbe_tx_context { 362 uint32_t hcksum_flags; 363 uint32_t ip_hdr_len; 364 uint32_t mac_hdr_len; 365 uint32_t l4_proto; 366 uint32_t mss; 367 uint32_t l4_hdr_len; 368 boolean_t lso_flag; 369 } ixgbe_tx_context_t; 370 371 /* 372 * Hold address/length of each DMA segment 373 */ 374 typedef struct sw_desc { 375 uint64_t address; 376 size_t length; 377 } sw_desc_t; 378 379 /* 380 * Handles and addresses of DMA buffer 381 */ 382 typedef struct dma_buffer { 383 caddr_t address; /* Virtual address */ 384 uint64_t dma_address; /* DMA (Hardware) address */ 385 ddi_acc_handle_t acc_handle; /* Data access handle */ 386 ddi_dma_handle_t dma_handle; /* DMA handle */ 387 size_t size; /* Buffer size */ 388 size_t len; /* Data length in the buffer */ 389 } dma_buffer_t; 390 391 /* 392 * Tx Control Block 393 */ 394 typedef struct tx_control_block { 395 single_link_t link; 396 uint32_t last_index; /* last descriptor of the pkt */ 397 uint32_t frag_num; 398 uint32_t desc_num; 399 mblk_t *mp; 400 tx_type_t tx_type; 401 ddi_dma_handle_t tx_dma_handle; 402 dma_buffer_t tx_buf; 403 sw_desc_t desc[MAX_COOKIE]; 404 } tx_control_block_t; 405 406 /* 407 * RX Control Block 408 */ 409 typedef struct rx_control_block { 410 mblk_t *mp; 411 uint32_t ref_cnt; 412 dma_buffer_t rx_buf; 413 frtn_t free_rtn; 414 struct ixgbe_rx_data *rx_data; 415 } rx_control_block_t; 416 417 /* 418 * Software Data Structure for Tx Ring 419 */ 420 typedef struct ixgbe_tx_ring { 421 uint32_t index; /* Ring index */ 422 uint32_t intr_vector; /* Interrupt vector index */ 423 uint32_t vect_bit; /* vector's bit in register */ 424 425 /* 426 * Mutexes 427 */ 428 kmutex_t tx_lock; 429 kmutex_t recycle_lock; 430 kmutex_t tcb_head_lock; 431 kmutex_t tcb_tail_lock; 432 433 /* 434 * Tx descriptor ring definitions 435 */ 436 dma_buffer_t tbd_area; 437 union ixgbe_adv_tx_desc *tbd_ring; 438 uint32_t tbd_head; /* Index of next tbd to recycle */ 439 uint32_t tbd_tail; /* Index of next tbd to transmit */ 440 uint32_t tbd_free; /* Number of free tbd */ 441 442 /* 443 * Tx control block list definitions 444 */ 445 tx_control_block_t *tcb_area; 446 tx_control_block_t **work_list; 447 tx_control_block_t **free_list; 448 uint32_t tcb_head; /* Head index of free list */ 449 uint32_t tcb_tail; /* Tail index of free list */ 450 uint32_t tcb_free; /* Number of free tcb in free list */ 451 452 uint32_t *tbd_head_wb; /* Head write-back */ 453 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 454 455 /* 456 * s/w context structure for TCP/UDP checksum offload 457 * and LSO. 458 */ 459 ixgbe_tx_context_t tx_context; 460 461 /* 462 * Tx ring settings and status 463 */ 464 uint32_t ring_size; /* Tx descriptor ring size */ 465 uint32_t free_list_size; /* Tx free list size */ 466 467 boolean_t reschedule; 468 uint32_t recycle_fail; 469 uint32_t stall_watchdog; 470 471 #ifdef IXGBE_DEBUG 472 /* 473 * Debug statistics 474 */ 475 uint32_t stat_overload; 476 uint32_t stat_fail_no_tbd; 477 uint32_t stat_fail_no_tcb; 478 uint32_t stat_fail_dma_bind; 479 uint32_t stat_reschedule; 480 uint32_t stat_break_tbd_limit; 481 uint32_t stat_lso_header_fail; 482 #endif 483 484 mac_ring_handle_t ring_handle; 485 486 /* 487 * Pointer to the ixgbe struct 488 */ 489 struct ixgbe *ixgbe; 490 } ixgbe_tx_ring_t; 491 492 /* 493 * Software Receive Ring 494 */ 495 typedef struct ixgbe_rx_data { 496 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 497 498 /* 499 * Rx descriptor ring definitions 500 */ 501 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 502 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 503 uint32_t rbd_next; /* Index of next rx desc */ 504 505 /* 506 * Rx control block list definitions 507 */ 508 rx_control_block_t *rcb_area; 509 rx_control_block_t **work_list; /* Work list of rcbs */ 510 rx_control_block_t **free_list; /* Free list of rcbs */ 511 uint32_t rcb_head; /* Index of next free rcb */ 512 uint32_t rcb_tail; /* Index to put recycled rcb */ 513 uint32_t rcb_free; /* Number of free rcbs */ 514 515 /* 516 * Rx sw ring settings and status 517 */ 518 uint32_t ring_size; /* Rx descriptor ring size */ 519 uint32_t free_list_size; /* Rx free list size */ 520 521 uint32_t rcb_pending; 522 uint32_t flag; 523 524 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */ 525 } ixgbe_rx_data_t; 526 527 /* 528 * Software Data Structure for Rx Ring 529 */ 530 typedef struct ixgbe_rx_ring { 531 uint32_t index; /* Ring index */ 532 uint32_t intr_vector; /* Interrupt vector index */ 533 uint32_t vect_bit; /* vector's bit in register */ 534 535 ixgbe_rx_data_t *rx_data; /* Rx software ring */ 536 537 kmutex_t rx_lock; /* Rx access lock */ 538 539 #ifdef IXGBE_DEBUG 540 /* 541 * Debug statistics 542 */ 543 uint32_t stat_frame_error; 544 uint32_t stat_cksum_error; 545 uint32_t stat_exceed_pkt; 546 #endif 547 548 mac_ring_handle_t ring_handle; 549 uint64_t ring_gen_num; 550 551 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 552 } ixgbe_rx_ring_t; 553 /* 554 * Software Receive Ring Group 555 */ 556 typedef struct ixgbe_rx_group { 557 uint32_t index; /* Group index */ 558 mac_group_handle_t group_handle; /* call back group handle */ 559 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 560 } ixgbe_rx_group_t; 561 562 /* 563 * structure to map interrupt cleanup to msi-x vector 564 */ 565 typedef struct ixgbe_intr_vector { 566 struct ixgbe *ixgbe; /* point to my adapter */ 567 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 568 int rxr_cnt; /* count rx rings */ 569 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 570 int txr_cnt; /* count tx rings */ 571 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 572 int other_cnt; /* count other interrupt */ 573 } ixgbe_intr_vector_t; 574 575 /* 576 * Software adapter state 577 */ 578 typedef struct ixgbe { 579 int instance; 580 mac_handle_t mac_hdl; 581 dev_info_t *dip; 582 struct ixgbe_hw hw; 583 struct ixgbe_osdep osdep; 584 585 adapter_info_t *capab; /* adapter hardware capabilities */ 586 ddi_taskq_t *lsc_taskq; /* link-status-change taskq */ 587 uint32_t eims; /* interrupt mask setting */ 588 uint32_t eimc; /* interrupt mask clear */ 589 uint32_t eicr; /* interrupt cause reg */ 590 591 uint32_t ixgbe_state; 592 link_state_t link_state; 593 uint32_t link_speed; 594 uint32_t link_duplex; 595 uint32_t link_down_timeout; 596 597 uint32_t reset_count; 598 uint32_t attach_progress; 599 uint32_t loopback_mode; 600 uint32_t default_mtu; 601 uint32_t max_frame_size; 602 603 uint32_t rcb_pending; 604 605 /* 606 * Each msi-x vector: map vector to interrupt cleanup 607 */ 608 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 609 610 /* 611 * Receive Rings 612 */ 613 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 614 uint32_t num_rx_rings; /* Number of rx rings in use */ 615 uint32_t rx_ring_size; /* Rx descriptor ring size */ 616 uint32_t rx_buf_size; /* Rx buffer size */ 617 618 /* 619 * Receive Groups 620 */ 621 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 622 uint32_t num_rx_groups; /* Number of rx groups in use */ 623 624 /* 625 * Transmit Rings 626 */ 627 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 628 uint32_t num_tx_rings; /* Number of tx rings in use */ 629 uint32_t tx_ring_size; /* Tx descriptor ring size */ 630 uint32_t tx_buf_size; /* Tx buffer size */ 631 632 boolean_t tx_ring_init; 633 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 634 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 635 boolean_t lso_enable; /* Large Segment Offload */ 636 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 637 uint32_t tx_copy_thresh; /* Tx copy threshold */ 638 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 639 uint32_t tx_overload_thresh; /* Tx overload threshold */ 640 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 641 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 642 uint32_t rx_copy_thresh; /* Rx copy threshold */ 643 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 644 uint32_t intr_throttling[MAX_INTR_VECTOR]; 645 uint32_t intr_force; 646 int fm_capabilities; /* FMA capabilities */ 647 648 int intr_type; 649 int intr_cnt; 650 int intr_cap; 651 size_t intr_size; 652 uint_t intr_pri; 653 ddi_intr_handle_t *htable; 654 uint32_t eims_mask; 655 656 kmutex_t gen_lock; /* General lock for device access */ 657 kmutex_t watchdog_lock; 658 kmutex_t rx_pending_lock; 659 660 boolean_t watchdog_enable; 661 boolean_t watchdog_start; 662 timeout_id_t watchdog_tid; 663 664 boolean_t unicst_init; 665 uint32_t unicst_avail; 666 uint32_t unicst_total; 667 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 668 uint32_t mcast_count; 669 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 670 671 ulong_t sys_page_size; 672 673 /* 674 * Kstat definitions 675 */ 676 kstat_t *ixgbe_ks; 677 678 uint32_t param_en_10000fdx_cap:1, 679 param_en_1000fdx_cap:1, 680 param_en_100fdx_cap:1, 681 param_adv_10000fdx_cap:1, 682 param_adv_1000fdx_cap:1, 683 param_adv_100fdx_cap:1, 684 param_pause_cap:1, 685 param_asym_pause_cap:1, 686 param_rem_fault:1, 687 param_adv_autoneg_cap:1, 688 param_adv_pause_cap:1, 689 param_adv_asym_pause_cap:1, 690 param_adv_rem_fault:1, 691 param_lp_10000fdx_cap:1, 692 param_lp_1000fdx_cap:1, 693 param_lp_100fdx_cap:1, 694 param_lp_autoneg_cap:1, 695 param_lp_pause_cap:1, 696 param_lp_asym_pause_cap:1, 697 param_lp_rem_fault:1, 698 param_pad_to_32:12; 699 } ixgbe_t; 700 701 typedef struct ixgbe_stat { 702 kstat_named_t link_speed; /* Link Speed */ 703 704 kstat_named_t reset_count; /* Reset Count */ 705 706 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 707 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 708 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 709 710 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 711 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 712 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 713 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 714 kstat_named_t tx_reschedule; /* Tx Reschedule */ 715 716 kstat_named_t gprc; /* Good Packets Received Count */ 717 kstat_named_t gptc; /* Good Packets Xmitted Count */ 718 kstat_named_t gor; /* Good Octets Received Count */ 719 kstat_named_t got; /* Good Octets Xmitd Count */ 720 kstat_named_t prc64; /* Packets Received - 64b */ 721 kstat_named_t prc127; /* Packets Received - 65-127b */ 722 kstat_named_t prc255; /* Packets Received - 127-255b */ 723 kstat_named_t prc511; /* Packets Received - 256-511b */ 724 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 725 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 726 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 727 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 728 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 729 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 730 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 731 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 732 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 733 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 734 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 735 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 736 737 kstat_named_t crcerrs; /* CRC Error Count */ 738 kstat_named_t illerrc; /* Illegal Byte Error Count */ 739 kstat_named_t errbc; /* Error Byte Count */ 740 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 741 kstat_named_t mpc; /* Missed Packets Count */ 742 kstat_named_t mlfc; /* MAC Local Fault Count */ 743 kstat_named_t mrfc; /* MAC Remote Fault Count */ 744 kstat_named_t rlec; /* Receive Length Error Count */ 745 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 746 kstat_named_t lxonrxc; /* Link XON Received Count */ 747 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 748 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 749 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 750 kstat_named_t mprc; /* Multicast Pkts Received Count */ 751 kstat_named_t rnbc; /* Receive No Buffers Count */ 752 kstat_named_t ruc; /* Receive Undersize Count */ 753 kstat_named_t rfc; /* Receive Frag Count */ 754 kstat_named_t roc; /* Receive Oversize Count */ 755 kstat_named_t rjc; /* Receive Jabber Count */ 756 kstat_named_t tor; /* Total Octets Recvd Count */ 757 kstat_named_t tot; /* Total Octets Xmitted Count */ 758 kstat_named_t tpr; /* Total Packets Received */ 759 kstat_named_t tpt; /* Total Packets Xmitted */ 760 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 761 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 762 } ixgbe_stat_t; 763 764 /* 765 * Function prototypes in ixgbe_buf.c 766 */ 767 int ixgbe_alloc_dma(ixgbe_t *); 768 void ixgbe_free_dma(ixgbe_t *); 769 void ixgbe_set_fma_flags(int, int); 770 void ixgbe_free_dma_buffer(dma_buffer_t *); 771 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring); 772 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data); 773 774 /* 775 * Function prototypes in ixgbe_main.c 776 */ 777 int ixgbe_start(ixgbe_t *, boolean_t); 778 void ixgbe_stop(ixgbe_t *, boolean_t); 779 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 780 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 781 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 782 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 783 784 void ixgbe_enable_watchdog_timer(ixgbe_t *); 785 void ixgbe_disable_watchdog_timer(ixgbe_t *); 786 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 787 788 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 789 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 790 void ixgbe_fm_ereport(ixgbe_t *, char *); 791 792 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 793 mac_ring_info_t *, mac_ring_handle_t); 794 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 795 mac_group_info_t *, mac_group_handle_t); 796 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 797 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 798 799 /* 800 * Function prototypes in ixgbe_gld.c 801 */ 802 int ixgbe_m_start(void *); 803 void ixgbe_m_stop(void *); 804 int ixgbe_m_promisc(void *, boolean_t); 805 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 806 int ixgbe_m_stat(void *, uint_t, uint64_t *); 807 void ixgbe_m_resources(void *); 808 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 809 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 810 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 811 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, 812 uint_t, uint_t, void *, uint_t *); 813 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *); 814 int ixgbe_get_priv_prop(ixgbe_t *, const char *, 815 uint_t, uint_t, void *, uint_t *); 816 boolean_t ixgbe_param_locked(mac_prop_id_t); 817 818 /* 819 * Function prototypes in ixgbe_rx.c 820 */ 821 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 822 void ixgbe_rx_recycle(caddr_t arg); 823 mblk_t *ixgbe_ring_rx_poll(void *, int); 824 825 /* 826 * Function prototypes in ixgbe_tx.c 827 */ 828 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 829 void ixgbe_free_tcb(tx_control_block_t *); 830 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 831 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 832 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 833 834 /* 835 * Function prototypes in ixgbe_log.c 836 */ 837 void ixgbe_notice(void *, const char *, ...); 838 void ixgbe_log(void *, const char *, ...); 839 void ixgbe_error(void *, const char *, ...); 840 841 /* 842 * Function prototypes in ixgbe_stat.c 843 */ 844 int ixgbe_init_stats(ixgbe_t *); 845 846 #ifdef __cplusplus 847 } 848 #endif 849 850 #endif /* _IXGBE_SW_H */ 851
Indexes created Tue Nov 24 05:22:20 UTC 2009
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