1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 29 * 30 * Power Management Support 31 * ------------------------ 32 * 33 * At the moment, the ahci driver only implements suspend/resume to 34 * support Suspend to RAM on X86 feature. Device power management isn't 35 * implemented, link power management is disabled, and hot plug isn't 36 * allowed during the period from suspend to resume. 37 * 38 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 39 * and DDI_RESUME entries, and don't need to take care of new requests 40 * sent down after suspend because the target driver (sd) has already 41 * handled these conditions, and blocked these requests. For the detailed 42 * information, please check with sdopen, sdclose and sdioctl routines. 43 * 44 */ 45 46 #include <sys/note.h> 47 #include <sys/scsi/scsi.h> 48 #include <sys/pci.h> 49 #include <sys/disp.h> 50 #include <sys/sata/sata_hba.h> 51 #include <sys/sata/adapters/ahci/ahcireg.h> 52 #include <sys/sata/adapters/ahci/ahcivar.h> 53 54 /* 55 * This is the string displayed by modinfo, etc. 56 * Make sure you keep the version ID up to date! 57 */ 58 static char ahci_ident[] = "ahci driver"; 59 60 /* 61 * Function prototypes for driver entry points 62 */ 63 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 64 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 65 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 66 static int ahci_quiesce(dev_info_t *); 67 68 /* 69 * Function prototypes for SATA Framework interfaces 70 */ 71 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 72 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 73 74 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 75 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 76 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 77 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 78 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 79 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 80 #if defined(__lock_lint) 81 static int ahci_selftest(dev_info_t *, sata_device_t *); 82 #endif 83 84 /* 85 * Local function prototypes 86 */ 87 static int ahci_alloc_ports_state(ahci_ctl_t *); 88 static void ahci_dealloc_ports_state(ahci_ctl_t *); 89 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 90 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 91 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 92 static void ahci_dealloc_rcvd_fis(ahci_port_t *); 93 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 95 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 96 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 97 static void ahci_alloc_pmult(ahci_ctl_t *, ahci_port_t *); 98 static void ahci_dealloc_pmult(ahci_ctl_t *, ahci_port_t *); 99 100 static int ahci_initialize_controller(ahci_ctl_t *); 101 static void ahci_uninitialize_controller(ahci_ctl_t *); 102 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 103 static int ahci_config_space_init(ahci_ctl_t *); 104 105 static void ahci_drain_ports_taskq(ahci_ctl_t *); 106 static int ahci_rdwr_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t *, 107 uint8_t); 108 static int ahci_read_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t *); 109 static int ahci_write_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t); 110 static int ahci_update_pmult_pscr(ahci_ctl_t *, ahci_addr_t *, 111 sata_device_t *); 112 static int ahci_update_pmult_gscr(ahci_ctl_t *, ahci_addr_t *, 113 sata_pmult_gscr_t *); 114 static int ahci_initialize_pmult(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *, 115 sata_device_t *); 116 static int ahci_initialize_pmport(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 117 static int ahci_probe_pmult(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 118 static int ahci_probe_pmport(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *, 119 sata_device_t *); 120 121 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 122 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 123 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, 124 ahci_addr_t *); 125 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 126 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 127 ahci_addr_t *, sata_pkt_t *); 128 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 129 ahci_addr_t *, sata_pkt_t *); 130 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, 131 ahci_addr_t *, int); 132 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 133 static void ahci_copy_ncq_err_page(sata_cmd_t *, 134 struct sata_ncq_error_recovery_page *); 135 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 136 137 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 138 static int ahci_hba_reset(ahci_ctl_t *); 139 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 140 static int ahci_pmport_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 141 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 142 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, 143 ahci_addr_t *); 144 static int ahci_reset_pmdevice_reject_pkts(ahci_ctl_t *, ahci_port_t *, 145 ahci_addr_t *); 146 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, 147 ahci_addr_t *); 148 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 149 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 150 uint8_t); 151 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 152 uint8_t, int, int *); 153 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 154 uint32_t, uint32_t, uint32_t, uint32_t); 155 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 156 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 157 uint8_t, sata_pkt_t *); 158 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 159 ahci_addr_t *, uint32_t); 160 static void ahci_pmult_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 161 uint8_t, uint32_t); 162 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 163 uint8_t, uint32_t); 164 static void ahci_events_handler(void *); 165 static void ahci_watchdog_handler(ahci_ctl_t *); 166 167 static uint_t ahci_intr(caddr_t, caddr_t); 168 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 169 static int ahci_add_intrs(ahci_ctl_t *, int); 170 static void ahci_rem_intrs(ahci_ctl_t *); 171 static void ahci_enable_all_intrs(ahci_ctl_t *); 172 static void ahci_disable_all_intrs(ahci_ctl_t *); 173 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 174 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 175 176 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 177 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 178 static int ahci_intr_ncq_events(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *); 179 static int ahci_intr_pmult_sntf_events(ahci_ctl_t *, ahci_port_t *, uint8_t); 180 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 181 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 182 ahci_port_t *, uint8_t); 183 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 184 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 185 uint8_t, uint32_t); 186 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 187 uint8_t, uint32_t); 188 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 189 190 static void ahci_get_ahci_addr(ahci_ctl_t *, sata_device_t *, ahci_addr_t *); 191 static int ahci_get_num_implemented_ports(uint32_t); 192 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 193 uint32_t); 194 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 195 #if AHCI_DEBUG 196 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 197 #endif 198 199 200 /* 201 * DMA attributes for the data buffer 202 * 203 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 204 * does not support 64-bit addressing 205 */ 206 static ddi_dma_attr_t buffer_dma_attr = { 207 DMA_ATTR_V0, /* dma_attr_version */ 208 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 209 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 210 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 211 0x2ull, /* dma_attr_align: word aligned */ 212 1, /* dma_attr_burstsizes */ 213 1, /* dma_attr_minxfer */ 214 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 215 0xffffffffull, /* dma_attr_seg */ 216 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 217 512, /* dma_attr_granular */ 218 0, /* dma_attr_flags */ 219 }; 220 221 /* 222 * DMA attributes for the rcvd FIS 223 * 224 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 225 * does not support 64-bit addressing 226 */ 227 static ddi_dma_attr_t rcvd_fis_dma_attr = { 228 DMA_ATTR_V0, /* dma_attr_version */ 229 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 230 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 231 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 232 0x100ull, /* dma_attr_align: 256-byte aligned */ 233 1, /* dma_attr_burstsizes */ 234 1, /* dma_attr_minxfer */ 235 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 236 0xffffffffull, /* dma_attr_seg */ 237 1, /* dma_attr_sgllen */ 238 1, /* dma_attr_granular */ 239 0, /* dma_attr_flags */ 240 }; 241 242 /* 243 * DMA attributes for the command list 244 * 245 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 246 * does not support 64-bit addressing 247 */ 248 static ddi_dma_attr_t cmd_list_dma_attr = { 249 DMA_ATTR_V0, /* dma_attr_version */ 250 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 251 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 252 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 253 0x400ull, /* dma_attr_align: 1K-byte aligned */ 254 1, /* dma_attr_burstsizes */ 255 1, /* dma_attr_minxfer */ 256 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 257 0xffffffffull, /* dma_attr_seg */ 258 1, /* dma_attr_sgllen */ 259 1, /* dma_attr_granular */ 260 0, /* dma_attr_flags */ 261 }; 262 263 /* 264 * DMA attributes for cmd tables 265 * 266 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 267 * does not support 64-bit addressing 268 */ 269 static ddi_dma_attr_t cmd_table_dma_attr = { 270 DMA_ATTR_V0, /* dma_attr_version */ 271 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 272 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 273 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 274 0x80ull, /* dma_attr_align: 128-byte aligned */ 275 1, /* dma_attr_burstsizes */ 276 1, /* dma_attr_minxfer */ 277 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 278 0xffffffffull, /* dma_attr_seg */ 279 1, /* dma_attr_sgllen */ 280 1, /* dma_attr_granular */ 281 0, /* dma_attr_flags */ 282 }; 283 284 285 /* Device access attributes */ 286 static ddi_device_acc_attr_t accattr = { 287 DDI_DEVICE_ATTR_V0, 288 DDI_STRUCTURE_LE_ACC, 289 DDI_STRICTORDER_ACC 290 }; 291 292 293 static struct dev_ops ahcictl_dev_ops = { 294 DEVO_REV, /* devo_rev */ 295 0, /* refcnt */ 296 ahci_getinfo, /* info */ 297 nulldev, /* identify */ 298 nulldev, /* probe */ 299 ahci_attach, /* attach */ 300 ahci_detach, /* detach */ 301 nodev, /* no reset */ 302 (struct cb_ops *)0, /* driver operations */ 303 NULL, /* bus operations */ 304 NULL, /* power */ 305 ahci_quiesce, /* quiesce */ 306 }; 307 308 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 309 SATA_TRAN_HOTPLUG_OPS_REV_1, 310 ahci_tran_hotplug_port_activate, 311 ahci_tran_hotplug_port_deactivate 312 }; 313 314 extern struct mod_ops mod_driverops; 315 316 static struct modldrv modldrv = { 317 &mod_driverops, /* driverops */ 318 ahci_ident, /* short description */ 319 &ahcictl_dev_ops, /* driver ops */ 320 }; 321 322 static struct modlinkage modlinkage = { 323 MODREV_1, 324 &modldrv, 325 NULL 326 }; 327 328 /* The following variables are watchdog handler related */ 329 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 330 static int ahci_watchdog_tick; 331 332 /* 333 * This static variable indicates the size of command table, 334 * and it's changeable with prdt number, which ahci_dma_prdt_number 335 * indicates. 336 */ 337 static size_t ahci_cmd_table_size; 338 339 /* 340 * The below global variables are tunable via /etc/system 341 * 342 * ahci_dma_prdt_number 343 * ahci_msi_enabled 344 * ahci_buf_64bit_dma 345 * ahci_commu_64bit_dma 346 */ 347 348 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 349 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 350 351 /* AHCI MSI is tunable */ 352 boolean_t ahci_msi_enabled = B_TRUE; 353 354 /* 355 * 64-bit dma addressing for data buffer is tunable 356 * 357 * The variable controls only the below value: 358 * DBAU (upper 32-bits physical address of data block) 359 */ 360 boolean_t ahci_buf_64bit_dma = B_TRUE; 361 362 /* 363 * 64-bit dma addressing for communication system descriptors is tunable 364 * 365 * The variable controls the below three values: 366 * 367 * PxCLBU (upper 32-bits for the command list base physical address) 368 * PxFBU (upper 32-bits for the received FIS base physical address) 369 * CTBAU (upper 32-bits of command table base) 370 */ 371 boolean_t ahci_commu_64bit_dma = B_TRUE; 372 373 /* 374 * By default, 64-bit dma for data buffer will be disabled for AMD/ATI SB600 375 * chipset. If the users want to have a try with 64-bit dma, please change 376 * the below variable value to enable it. 377 */ 378 boolean_t sb600_buf_64bit_dma_disable = B_TRUE; 379 380 /* 381 * By default, 64-bit dma for command buffer will be disabled for AMD/ATI 382 * SB600/700/710/750/800. If the users want to have a try with 64-bit dma, 383 * please change the below value to enable it. 384 */ 385 boolean_t sbxxx_commu_64bit_dma_disable = B_TRUE; 386 387 388 /* 389 * End of global tunable variable definition 390 */ 391 392 #if AHCI_DEBUG 393 uint32_t ahci_debug_flags = 0; 394 #else 395 uint32_t ahci_debug_flags = (AHCIDBG_ERRS|AHCIDBG_TIMEOUT); 396 #endif 397 398 399 #if AHCI_DEBUG 400 /* The following is needed for ahci_log() */ 401 static kmutex_t ahci_log_mutex; 402 static char ahci_log_buf[512]; 403 #endif 404 405 /* Opaque state pointer initialized by ddi_soft_state_init() */ 406 static void *ahci_statep = NULL; 407 408 /* 409 * ahci module initialization. 410 */ 411 int 412 _init(void) 413 { 414 int ret; 415 416 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 417 if (ret != 0) { 418 goto err_out; 419 } 420 421 #if AHCI_DEBUG 422 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 423 #endif 424 425 if ((ret = sata_hba_init(&modlinkage)) != 0) { 426 #if AHCI_DEBUG 427 mutex_destroy(&ahci_log_mutex); 428 #endif 429 ddi_soft_state_fini(&ahci_statep); 430 goto err_out; 431 } 432 433 ret = mod_install(&modlinkage); 434 if (ret != 0) { 435 sata_hba_fini(&modlinkage); 436 #if AHCI_DEBUG 437 mutex_destroy(&ahci_log_mutex); 438 #endif 439 ddi_soft_state_fini(&ahci_statep); 440 goto err_out; 441 } 442 443 /* watchdog tick */ 444 ahci_watchdog_tick = drv_usectohz( 445 (clock_t)ahci_watchdog_timeout * 1000000); 446 return (ret); 447 448 err_out: 449 cmn_err(CE_WARN, "!ahci: Module init failed"); 450 return (ret); 451 } 452 453 /* 454 * ahci module uninitialize. 455 */ 456 int 457 _fini(void) 458 { 459 int ret; 460 461 ret = mod_remove(&modlinkage); 462 if (ret != 0) { 463 return (ret); 464 } 465 466 /* Remove the resources allocated in _init(). */ 467 sata_hba_fini(&modlinkage); 468 #if AHCI_DEBUG 469 mutex_destroy(&ahci_log_mutex); 470 #endif 471 ddi_soft_state_fini(&ahci_statep); 472 473 return (ret); 474 } 475 476 /* 477 * _info entry point 478 */ 479 int 480 _info(struct modinfo *modinfop) 481 { 482 return (mod_info(&modlinkage, modinfop)); 483 } 484 485 /* 486 * The attach entry point for dev_ops. 487 */ 488 static int 489 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 490 { 491 ahci_ctl_t *ahci_ctlp = NULL; 492 int instance = ddi_get_instance(dip); 493 int status; 494 int attach_state; 495 uint32_t cap_status, ahci_version; 496 int intr_types; 497 int i; 498 pci_regspec_t *regs; 499 int regs_length; 500 int rnumber; 501 #if AHCI_DEBUG 502 int speed; 503 #endif 504 505 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "ahci_attach enter", 506 NULL); 507 508 switch (cmd) { 509 case DDI_ATTACH: 510 break; 511 512 case DDI_RESUME: 513 514 /* 515 * During DDI_RESUME, the hardware state of the device 516 * (power may have been removed from the device) must be 517 * restored, allow pending requests to continue, and 518 * service new requests. 519 */ 520 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 521 mutex_enter(&ahci_ctlp->ahcictl_mutex); 522 523 /* Restart watch thread */ 524 if (ahci_ctlp->ahcictl_timeout_id == 0) 525 ahci_ctlp->ahcictl_timeout_id = timeout( 526 (void (*)(void *))ahci_watchdog_handler, 527 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 528 529 mutex_exit(&ahci_ctlp->ahcictl_mutex); 530 531 /* 532 * Re-initialize the controller and enable the interrupts and 533 * restart all the ports. 534 * 535 * Note that so far we don't support hot-plug during 536 * suspend/resume. 537 */ 538 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 539 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 540 "Failed to initialize the controller " 541 "during DDI_RESUME", NULL); 542 return (DDI_FAILURE); 543 } 544 545 mutex_enter(&ahci_ctlp->ahcictl_mutex); 546 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 547 mutex_exit(&ahci_ctlp->ahcictl_mutex); 548 549 return (DDI_SUCCESS); 550 551 default: 552 return (DDI_FAILURE); 553 } 554 555 attach_state = AHCI_ATTACH_STATE_NONE; 556 557 /* Allocate soft state */ 558 status = ddi_soft_state_zalloc(ahci_statep, instance); 559 if (status != DDI_SUCCESS) { 560 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 561 instance); 562 goto err_out; 563 } 564 565 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 566 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 567 ahci_ctlp->ahcictl_dip = dip; 568 569 /* Initialize the cport/port mapping */ 570 for (i = 0; i < AHCI_MAX_PORTS; i++) { 571 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 572 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 573 } 574 575 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 576 577 /* 578 * Now map the AHCI base address; which includes global 579 * registers and port control registers 580 * 581 * According to the spec, the AHCI Base Address is BAR5, 582 * but BAR0-BAR4 are optional, so we need to check which 583 * rnumber is used for BAR5. 584 */ 585 586 /* 587 * search through DDI "reg" property for the AHCI register set 588 */ 589 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 590 DDI_PROP_DONTPASS, "reg", (int **)®s, 591 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 592 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 593 instance); 594 goto err_out; 595 } 596 597 /* AHCI Base Address is located at 0x24 offset */ 598 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 599 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 600 == AHCI_PCI_RNUM) 601 break; 602 } 603 604 ddi_prop_free(regs); 605 606 if (rnumber == regs_length) { 607 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 608 instance); 609 goto err_out; 610 } 611 612 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 613 614 status = ddi_regs_map_setup(dip, 615 rnumber, 616 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 617 0, 618 0, 619 &accattr, 620 &ahci_ctlp->ahcictl_ahci_acc_handle); 621 if (status != DDI_SUCCESS) { 622 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 623 instance); 624 goto err_out; 625 } 626 627 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 628 629 /* Get the AHCI version information */ 630 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 631 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 632 633 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 634 (ahci_version & 0xffff0000) >> 16, 635 ((ahci_version & 0x0000ff00) >> 4 | 636 (ahci_version & 0x000000ff))); 637 638 /* We don't support controllers whose versions are lower than 1.0 */ 639 if (!(ahci_version & 0xffff0000)) { 640 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 641 "than version 1.0", instance); 642 goto err_out; 643 } 644 645 /* Get the HBA capabilities information */ 646 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 647 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 648 649 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba capabilities = 0x%x", 650 cap_status); 651 652 #if AHCI_DEBUG 653 /* Get the interface speed supported by the HBA */ 654 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 655 if (speed == 0x01) { 656 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 657 "hba interface speed support: Gen 1 (1.5Gbps)", NULL); 658 } else if (speed == 0x10) { 659 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 660 "hba interface speed support: Gen 2 (3 Gbps)", NULL); 661 } else if (speed == 0x11) { 662 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 663 "hba interface speed support: Gen 3 (6 Gbps)", NULL); 664 } 665 #endif 666 667 /* Get the number of command slots supported by the HBA */ 668 ahci_ctlp->ahcictl_num_cmd_slots = 669 ((cap_status & AHCI_HBA_CAP_NCS) >> 670 AHCI_HBA_CAP_NCS_SHIFT) + 1; 671 672 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 673 ahci_ctlp->ahcictl_num_cmd_slots); 674 675 /* Get the bit map which indicates ports implemented by the HBA */ 676 ahci_ctlp->ahcictl_ports_implemented = 677 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 678 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 679 680 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 681 ahci_ctlp->ahcictl_ports_implemented); 682 683 /* 684 * According to the AHCI spec, CAP.NP should indicate the maximum 685 * number of ports supported by the HBA silicon, but we found 686 * this value of ICH8 chipset only indicates the number of ports 687 * implemented (exposed) by it. Therefore, the driver should calculate 688 * the potential maximum value by checking PI register, and use 689 * the maximum of this value and CAP.NP. 690 */ 691 ahci_ctlp->ahcictl_num_ports = max( 692 (cap_status & AHCI_HBA_CAP_NP) + 1, 693 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 694 695 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 696 ahci_ctlp->ahcictl_num_ports); 697 698 /* Get the number of implemented ports by the HBA */ 699 ahci_ctlp->ahcictl_num_implemented_ports = 700 ahci_get_num_implemented_ports( 701 ahci_ctlp->ahcictl_ports_implemented); 702 703 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 704 "hba number of implemented ports: %d", 705 ahci_ctlp->ahcictl_num_implemented_ports); 706 707 /* Check whether HBA supports 64bit DMA addressing */ 708 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 709 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA; 710 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA; 711 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 712 "hba does not support 64-bit addressing", NULL); 713 } 714 715 /* Checking for the support of Port Multiplier */ 716 if (cap_status & AHCI_HBA_CAP_SPM) { 717 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PMULT_CBSS; 718 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp, 719 "hba supports port multiplier (CBSS)", NULL); 720 721 /* Support FIS-based switching ? */ 722 if (cap_status & AHCI_HBA_CAP_FBSS) { 723 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PMULT_FBSS; 724 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp, 725 "hba supports FIS-based switching (FBSS)", NULL); 726 } 727 } 728 729 /* Checking for Support Command List Override */ 730 if (cap_status & AHCI_HBA_CAP_SCLO) { 731 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SCLO; 732 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp, 733 "hba supports command list override.", NULL); 734 } 735 736 /* Checking for Asynchronous Notification */ 737 if (cap_status & AHCI_HBA_CAP_SSNTF) { 738 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SNTF; 739 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp, 740 "hba supports asynchronous notification.", NULL); 741 } 742 743 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 744 != DDI_SUCCESS) { 745 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 746 instance); 747 goto err_out; 748 } 749 750 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 751 752 /* 753 * Check the pci configuration space, and set caps. We also 754 * handle the hardware defect in this function. 755 * 756 * For example, force ATI SB600 to use 32-bit dma addressing 757 * since it doesn't support 64-bit dma though its CAP register 758 * declares it support. 759 */ 760 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 761 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 762 instance); 763 goto err_out; 764 } 765 766 /* 767 * Disable the whole controller interrupts before adding 768 * interrupt handlers(s). 769 */ 770 ahci_disable_all_intrs(ahci_ctlp); 771 772 /* Get supported interrupt types */ 773 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 774 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 775 instance); 776 goto err_out; 777 } 778 779 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 780 "ddi_intr_get_supported_types() returned: 0x%x", 781 intr_types); 782 783 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 784 /* 785 * Try MSI first, but fall back to FIXED if failed 786 */ 787 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_MSI) == 788 DDI_SUCCESS) { 789 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 790 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 791 "Using MSI interrupt type", NULL); 792 goto intr_done; 793 } 794 795 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 796 "MSI registration failed, " 797 "trying FIXED interrupts", NULL); 798 } 799 800 if (intr_types & DDI_INTR_TYPE_FIXED) { 801 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_FIXED) == 802 DDI_SUCCESS) { 803 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 804 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 805 "Using FIXED interrupt type", NULL); 806 goto intr_done; 807 } 808 809 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 810 "FIXED interrupt registration failed", NULL); 811 } 812 813 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 814 815 goto err_out; 816 817 intr_done: 818 819 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 820 821 /* Initialize the controller mutex */ 822 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 823 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 824 825 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 826 827 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 828 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 829 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 830 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 831 } 832 833 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 834 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 835 sizeof (ahci_prdt_item_t)); 836 837 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 838 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 839 " ahci_cmd_table_size is 0x%x", 840 ahci_dma_prdt_number, ahci_cmd_table_size); 841 842 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 843 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 844 ahci_dma_prdt_number; 845 846 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 847 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 848 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 849 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 850 851 /* 852 * enable 64bit dma for data buffer for SB600 if 853 * sb600_buf_64bit_dma_disable is B_FALSE 854 */ 855 if ((ahci_buf_64bit_dma == B_FALSE) || 856 ((ahci_ctlp->ahcictl_cap & AHCI_CAP_BUF_32BIT_DMA) && 857 !(sb600_buf_64bit_dma_disable == B_FALSE && 858 ahci_ctlp->ahcictl_venid == 0x1002 && 859 ahci_ctlp->ahcictl_devid == 0x4380))) { 860 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 861 0xffffffffull; 862 } 863 864 /* 865 * enable 64bit dma for command buffer for SB600/700/710/800 866 * if sbxxx_commu_64bit_dma_disable is B_FALSE 867 */ 868 if ((ahci_commu_64bit_dma == B_FALSE) || 869 ((ahci_ctlp->ahcictl_cap & AHCI_CAP_COMMU_32BIT_DMA) && 870 !(sbxxx_commu_64bit_dma_disable == B_FALSE && 871 ahci_ctlp->ahcictl_venid == 0x1002 && 872 (ahci_ctlp->ahcictl_devid == 0x4380 || 873 ahci_ctlp->ahcictl_devid == 0x4391)))) { 874 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 875 0xffffffffull; 876 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 877 0xffffffffull; 878 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 879 0xffffffffull; 880 } 881 882 /* Allocate the ports structure */ 883 status = ahci_alloc_ports_state(ahci_ctlp); 884 if (status != AHCI_SUCCESS) { 885 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 886 instance); 887 goto err_out; 888 } 889 890 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 891 892 /* 893 * Initialize the controller and ports. 894 */ 895 status = ahci_initialize_controller(ahci_ctlp); 896 if (status != AHCI_SUCCESS) { 897 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 898 instance); 899 goto err_out; 900 } 901 902 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 903 904 /* Start one thread to check packet timeouts */ 905 ahci_ctlp->ahcictl_timeout_id = timeout( 906 (void (*)(void *))ahci_watchdog_handler, 907 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 908 909 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 910 911 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 912 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 913 instance); 914 goto err_out; 915 } 916 917 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 918 919 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!", NULL); 920 921 return (DDI_SUCCESS); 922 923 err_out: 924 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 925 mutex_enter(&ahci_ctlp->ahcictl_mutex); 926 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 927 ahci_ctlp->ahcictl_timeout_id = 0; 928 mutex_exit(&ahci_ctlp->ahcictl_mutex); 929 } 930 931 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 932 ahci_uninitialize_controller(ahci_ctlp); 933 } 934 935 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 936 ahci_dealloc_ports_state(ahci_ctlp); 937 } 938 939 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 940 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 941 } 942 943 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 944 ahci_rem_intrs(ahci_ctlp); 945 } 946 947 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 948 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 949 } 950 951 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 952 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 953 } 954 955 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 956 ddi_soft_state_free(ahci_statep, instance); 957 } 958 959 return (DDI_FAILURE); 960 } 961 962 /* 963 * The detach entry point for dev_ops. 964 */ 965 static int 966 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 967 { 968 ahci_ctl_t *ahci_ctlp; 969 int instance; 970 int ret; 971 972 instance = ddi_get_instance(dip); 973 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 974 975 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter", NULL); 976 977 switch (cmd) { 978 case DDI_DETACH: 979 980 /* disable the interrupts for an uninterrupted detach */ 981 mutex_enter(&ahci_ctlp->ahcictl_mutex); 982 ahci_disable_all_intrs(ahci_ctlp); 983 mutex_exit(&ahci_ctlp->ahcictl_mutex); 984 985 /* unregister from the sata framework. */ 986 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 987 if (ret != AHCI_SUCCESS) { 988 mutex_enter(&ahci_ctlp->ahcictl_mutex); 989 ahci_enable_all_intrs(ahci_ctlp); 990 mutex_exit(&ahci_ctlp->ahcictl_mutex); 991 return (DDI_FAILURE); 992 } 993 994 mutex_enter(&ahci_ctlp->ahcictl_mutex); 995 996 /* stop the watchdog handler */ 997 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 998 ahci_ctlp->ahcictl_timeout_id = 0; 999 1000 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1001 1002 /* uninitialize the controller */ 1003 ahci_uninitialize_controller(ahci_ctlp); 1004 1005 /* remove the interrupts */ 1006 ahci_rem_intrs(ahci_ctlp); 1007 1008 /* deallocate the ports structures */ 1009 ahci_dealloc_ports_state(ahci_ctlp); 1010 1011 /* destroy mutex */ 1012 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 1013 1014 /* teardown the pci config */ 1015 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 1016 1017 /* remove the reg maps. */ 1018 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 1019 1020 /* free the soft state. */ 1021 ddi_soft_state_free(ahci_statep, instance); 1022 1023 return (DDI_SUCCESS); 1024 1025 case DDI_SUSPEND: 1026 1027 /* 1028 * The steps associated with suspension must include putting 1029 * the underlying device into a quiescent state so that it 1030 * will not generate interrupts or modify or access memory. 1031 */ 1032 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1033 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 1034 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1035 return (DDI_SUCCESS); 1036 } 1037 1038 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 1039 1040 /* stop the watchdog handler */ 1041 if (ahci_ctlp->ahcictl_timeout_id) { 1042 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 1043 ahci_ctlp->ahcictl_timeout_id = 0; 1044 } 1045 1046 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1047 1048 /* 1049 * drain the taskq 1050 */ 1051 ahci_drain_ports_taskq(ahci_ctlp); 1052 1053 /* 1054 * Disable the interrupts and stop all the ports. 1055 */ 1056 ahci_uninitialize_controller(ahci_ctlp); 1057 1058 return (DDI_SUCCESS); 1059 1060 default: 1061 return (DDI_FAILURE); 1062 } 1063 } 1064 1065 /* 1066 * The info entry point for dev_ops. 1067 * 1068 */ 1069 static int 1070 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 1071 void *arg, void **result) 1072 { 1073 #ifndef __lock_lint 1074 _NOTE(ARGUNUSED(dip)) 1075 #endif /* __lock_lint */ 1076 1077 ahci_ctl_t *ahci_ctlp; 1078 int instance; 1079 dev_t dev; 1080 1081 dev = (dev_t)arg; 1082 instance = getminor(dev); 1083 1084 switch (infocmd) { 1085 case DDI_INFO_DEVT2DEVINFO: 1086 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1087 if (ahci_ctlp != NULL) { 1088 *result = ahci_ctlp->ahcictl_dip; 1089 return (DDI_SUCCESS); 1090 } else { 1091 *result = NULL; 1092 return (DDI_FAILURE); 1093 } 1094 case DDI_INFO_DEVT2INSTANCE: 1095 *(int *)result = instance; 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 return (DDI_SUCCESS); 1102 } 1103 1104 /* 1105 * Registers the ahci with sata framework. 1106 */ 1107 static int 1108 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 1109 { 1110 struct sata_hba_tran *sata_hba_tran; 1111 1112 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 1113 "ahci_register_sata_hba_tran enter", NULL); 1114 1115 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1116 1117 /* Allocate memory for the sata_hba_tran */ 1118 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 1119 1120 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 1121 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 1122 sata_hba_tran->sata_tran_hba_dma_attr = 1123 &ahci_ctlp->ahcictl_buffer_dma_attr; 1124 1125 /* Report the number of implemented ports */ 1126 sata_hba_tran->sata_tran_hba_num_cports = 1127 ahci_ctlp->ahcictl_num_implemented_ports; 1128 1129 /* Support ATAPI device */ 1130 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1131 1132 /* Get the data transfer capability for PIO command by the HBA */ 1133 if (cap_status & AHCI_HBA_CAP_PMD) { 1134 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1135 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1136 "DRQ block data transfer for PIO command protocol", NULL); 1137 } 1138 1139 /* 1140 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1141 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1142 * QUEUED (EXT), and SERVICE commands). Queued operations are 1143 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1144 * QUEUED commands when the HBA and device support native command 1145 * queuing(NCQ). 1146 * 1147 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1148 * CAP register of the HBA indicates NCQ is supported. 1149 * 1150 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1151 * set because the previous register content of PxCI can be re-written 1152 * in the register write. 1153 */ 1154 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1155 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1156 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1157 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1158 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1159 "Command Queuing", NULL); 1160 } 1161 1162 /* Support port multiplier? */ 1163 if (cap_status & AHCI_HBA_CAP_SPM) { 1164 sata_hba_tran->sata_tran_hba_features_support |= 1165 SATA_CTLF_PORT_MULTIPLIER; 1166 1167 /* Support FIS-based switching for port multiplier? */ 1168 if (cap_status & AHCI_HBA_CAP_FBSS) { 1169 sata_hba_tran->sata_tran_hba_features_support |= 1170 SATA_CTLF_PMULT_FBS; 1171 } 1172 } 1173 1174 /* Report the number of command slots */ 1175 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1176 1177 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1178 sata_hba_tran->sata_tran_start = ahci_tran_start; 1179 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1180 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1181 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1182 #ifdef __lock_lint 1183 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1184 #endif 1185 /* 1186 * When SATA framework adds support for pwrmgt the 1187 * pwrmgt_ops needs to be updated 1188 */ 1189 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1190 sata_hba_tran->sata_tran_ioctl = NULL; 1191 1192 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1193 1194 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1195 1196 /* Attach it to SATA framework */ 1197 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1198 != DDI_SUCCESS) { 1199 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1200 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1201 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1202 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1203 return (AHCI_FAILURE); 1204 } 1205 1206 return (AHCI_SUCCESS); 1207 } 1208 1209 /* 1210 * Unregisters the ahci with sata framework. 1211 */ 1212 static int 1213 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1214 { 1215 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 1216 "ahci_unregister_sata_hba_tran enter", NULL); 1217 1218 /* Detach from the SATA framework. */ 1219 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1220 DDI_SUCCESS) { 1221 return (AHCI_FAILURE); 1222 } 1223 1224 /* Deallocate sata_hba_tran. */ 1225 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1226 sizeof (sata_hba_tran_t)); 1227 1228 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1229 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1230 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1231 1232 return (AHCI_SUCCESS); 1233 } 1234 1235 #define SET_PORTSTR(str, addrp) \ 1236 if (AHCI_ADDR_IS_PORT(addrp)) \ 1237 (void) sprintf((str), "%d", (addrp)->aa_port); \ 1238 else if (AHCI_ADDR_IS_PMULT(addrp)) \ 1239 (void) sprintf((str), "%d (pmult)", (addrp)->aa_port); \ 1240 else \ 1241 (void) sprintf((str), "%d:%d", (addrp)->aa_port, \ 1242 (addrp)->aa_pmport); 1243 1244 /* 1245 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1246 * port status registers and an attached device type via sata_device 1247 * structure. 1248 * 1249 * We return the cached information from a previous hardware probe. The 1250 * actual hardware probing itself was done either from within 1251 * ahci_initialize_controller() during the driver attach or from a phy 1252 * ready change interrupt handler. 1253 */ 1254 static int 1255 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1256 { 1257 ahci_ctl_t *ahci_ctlp; 1258 ahci_port_t *ahci_portp; 1259 ahci_addr_t addr, pmult_addr; 1260 uint8_t cport = sd->satadev_addr.cport; 1261 char portstr[10]; 1262 uint8_t device_type; 1263 uint32_t port_state; 1264 uint8_t port; 1265 int rval = SATA_SUCCESS, rval_init; 1266 1267 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1268 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1269 1270 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1271 1272 mutex_enter(&ahci_portp->ahciport_mutex); 1273 1274 ahci_get_ahci_addr(ahci_ctlp, sd, &addr); 1275 ASSERT(AHCI_ADDR_IS_VALID(&addr)); 1276 SET_PORTSTR(portstr, &addr); 1277 1278 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 1279 "ahci_tran_probe_port enter: port %s", portstr); 1280 1281 if ((AHCI_ADDR_IS_PMULT(&addr) || AHCI_ADDR_IS_PMPORT(&addr)) && 1282 (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT || 1283 ahci_portp->ahciport_pmult_info == NULL)) { 1284 /* port mutliplier is removed. */ 1285 AHCIDBG(AHCIDBG_PMULT, ahci_ctlp, 1286 "ahci_tran_probe_port: " 1287 "pmult is removed from port %s", portstr); 1288 mutex_exit(&ahci_portp->ahciport_mutex); 1289 return (SATA_FAILURE); 1290 } 1291 1292 /* 1293 * The sata_device may refer to 1294 * 1. A controller port. 1295 * A controller port should be ready here. 1296 * 2. A port multiplier. 1297 * SATA_ADDR_PMULT_SPEC - if it is not initialized yet, initialize 1298 * it and register the port multiplier to the framework. 1299 * SATA_ADDR_PMULT - check the status of all its device ports. 1300 * 3. A port multiplier port. 1301 * If it has not been initialized, initialized it. 1302 * 1303 * A port multiplier or a port multiplier port may require some 1304 * initialization because we cannot do these time-consuming jobs in an 1305 * interrupt context. 1306 */ 1307 if (sd->satadev_addr.qual & SATA_ADDR_PMULT_SPEC) { 1308 AHCI_ADDR_SET_PMULT(&pmult_addr, port); 1309 /* Initialize registers on a port multiplier */ 1310 rval_init = ahci_initialize_pmult(ahci_ctlp, 1311 ahci_portp, &pmult_addr, sd); 1312 if (rval_init != AHCI_SUCCESS) { 1313 AHCIDBG(AHCIDBG_PMULT, ahci_ctlp, 1314 "ahci_tran_probe_port: " 1315 "pmult initialization failed.", NULL); 1316 mutex_exit(&ahci_portp->ahciport_mutex); 1317 return (SATA_FAILURE); 1318 } 1319 } else if (sd->satadev_addr.qual & SATA_ADDR_PMULT) { 1320 /* Check pmports hotplug events */ 1321 (void) ahci_probe_pmult(ahci_ctlp, ahci_portp, &addr); 1322 } else if (sd->satadev_addr.qual & (SATA_ADDR_PMPORT | 1323 SATA_ADDR_DPMPORT)) { 1324 if (ahci_probe_pmport(ahci_ctlp, ahci_portp, 1325 &addr, sd) != AHCI_SUCCESS) { 1326 rval = SATA_FAILURE; 1327 goto out; 1328 } 1329 } 1330 1331 /* Update port state and device type */ 1332 port_state = AHCIPORT_GET_STATE(ahci_portp, &addr); 1333 1334 switch (port_state) { 1335 1336 case SATA_PSTATE_FAILED: 1337 sd->satadev_state = SATA_PSTATE_FAILED; 1338 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1339 "ahci_tran_probe_port: port %s PORT FAILED", portstr); 1340 goto out; 1341 1342 case SATA_PSTATE_SHUTDOWN: 1343 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1344 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1345 "ahci_tran_probe_port: port %s PORT SHUTDOWN", portstr); 1346 goto out; 1347 1348 case SATA_PSTATE_PWROFF: 1349 sd->satadev_state = SATA_PSTATE_PWROFF; 1350 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1351 "ahci_tran_probe_port: port %s PORT PWROFF", portstr); 1352 goto out; 1353 1354 case SATA_PSTATE_PWRON: 1355 sd->satadev_state = SATA_PSTATE_PWRON; 1356 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1357 "ahci_tran_probe_port: port %s PORT PWRON", portstr); 1358 break; 1359 1360 default: 1361 sd->satadev_state = port_state; 1362 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1363 "ahci_tran_probe_port: port %s PORT NORMAL %x", 1364 portstr, port_state); 1365 break; 1366 } 1367 1368 device_type = AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr); 1369 1370 switch (device_type) { 1371 1372 case SATA_DTYPE_ATADISK: 1373 sd->satadev_type = SATA_DTYPE_ATADISK; 1374 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1375 "ahci_tran_probe_port: port %s DISK found", portstr); 1376 break; 1377 1378 case SATA_DTYPE_ATAPI: 1379 /* 1380 * HBA driver only knows it's an ATAPI device, and don't know 1381 * it's CD/DVD, tape or ATAPI disk because the ATAPI device 1382 * type need to be determined by checking IDENTIFY PACKET 1383 * DEVICE data 1384 */ 1385 sd->satadev_type = SATA_DTYPE_ATAPI; 1386 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1387 "ahci_tran_probe_port: port %s ATAPI found", portstr); 1388 break; 1389 1390 case SATA_DTYPE_PMULT: 1391 ASSERT(AHCI_ADDR_IS_PORT(&addr)||AHCI_ADDR_IS_PMULT(&addr)); 1392 sd->satadev_type = SATA_DTYPE_PMULT; 1393 1394 /* Update the number of pmports. */ 1395 ASSERT(ahci_portp->ahciport_pmult_info != NULL); 1396 sd->satadev_add_info = ahci_portp-> 1397 ahciport_pmult_info->ahcipmi_num_dev_ports; 1398 1399 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1400 "ahci_tran_probe_port: port %s Port Multiplier found", 1401 portstr); 1402 break; 1403 1404 case SATA_DTYPE_UNKNOWN: 1405 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1406 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1407 "ahci_tran_probe_port: port %s Unknown device found", 1408 portstr); 1409 break; 1410 1411 default: 1412 /* we don't support any other device types */ 1413 sd->satadev_type = SATA_DTYPE_NONE; 1414 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1415 "ahci_tran_probe_port: port %s No device found", portstr); 1416 break; 1417 } 1418 1419 out: 1420 /* Register update only fails while probing a pmult/pmport */ 1421 if (AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMULT(&addr)) { 1422 ahci_update_sata_registers(ahci_ctlp, port, sd); 1423 } else if (AHCI_ADDR_IS_PMPORT(&addr)) { 1424 if (port_state & SATA_STATE_READY) 1425 if (ahci_update_pmult_pscr(ahci_ctlp, 1426 &addr, sd) != AHCI_SUCCESS) 1427 rval = SATA_FAILURE; 1428 } 1429 1430 mutex_exit(&ahci_portp->ahciport_mutex); 1431 return (rval); 1432 } 1433 1434 /* 1435 * There are four operation modes in sata framework: 1436 * SATA_OPMODE_INTERRUPTS 1437 * SATA_OPMODE_POLLING 1438 * SATA_OPMODE_ASYNCH 1439 * SATA_OPMODE_SYNCH 1440 * 1441 * Their combined meanings as following: 1442 * 1443 * SATA_OPMODE_SYNCH 1444 * The command has to be completed before sata_tran_start functions returns. 1445 * Either interrupts or polling could be used - it's up to the driver. 1446 * Mode used currently for internal, sata-module initiated operations. 1447 * 1448 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1449 * It is the same as the one above. 1450 * 1451 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1452 * The command has to be completed before sata_tran_start function returns. 1453 * No interrupt used, polling only. This should be the mode used for scsi 1454 * packets with FLAG_NOINTR. 1455 * 1456 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1457 * The command may be queued (callback function specified). Interrupts could 1458 * be used. It's normal operation mode. 1459 */ 1460 /* 1461 * Called by sata framework to transport a sata packet down stream. 1462 */ 1463 static int 1464 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1465 { 1466 ahci_ctl_t *ahci_ctlp; 1467 ahci_port_t *ahci_portp; 1468 ahci_addr_t addr; 1469 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1470 uint8_t port; 1471 char portstr[10]; 1472 1473 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1474 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1475 1476 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 1477 "ahci_tran_start enter: cport %d satapkt 0x%p", 1478 cport, (void *)spkt); 1479 1480 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1481 1482 mutex_enter(&ahci_portp->ahciport_mutex); 1483 ahci_get_ahci_addr(ahci_ctlp, &spkt->satapkt_device, &addr); 1484 SET_PORTSTR(portstr, &addr); 1485 1486 /* Sanity check */ 1487 if (AHCI_ADDR_IS_PMPORT(&addr)) { 1488 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT || 1489 ahci_portp->ahciport_pmult_info == NULL) { 1490 1491 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1492 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1493 spkt->satapkt_device.satadev_state = SATA_STATE_UNKNOWN; 1494 ahci_update_sata_registers(ahci_ctlp, port, 1495 &spkt->satapkt_device); 1496 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1497 "ahci_tran_start returning PORT_ERROR while " 1498 "pmult removed: port: %s", portstr); 1499 mutex_exit(&ahci_portp->ahciport_mutex); 1500 return (SATA_TRAN_PORT_ERROR); 1501 } 1502 1503 if (!(AHCIPORT_GET_STATE(ahci_portp, &addr) & 1504 SATA_STATE_READY)) { 1505 if (!ddi_in_panic() || 1506 ahci_initialize_pmport(ahci_ctlp, 1507 ahci_portp, &addr) != AHCI_SUCCESS) { 1508 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1509 spkt->satapkt_device.satadev_type = 1510 AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr); 1511 spkt->satapkt_device.satadev_state = 1512 AHCIPORT_GET_STATE(ahci_portp, &addr); 1513 ahci_update_sata_registers(ahci_ctlp, port, 1514 &spkt->satapkt_device); 1515 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1516 "ahci_tran_start returning PORT_ERROR " 1517 "while sub-link is not initialized " 1518 "at port: %s", portstr); 1519 mutex_exit(&ahci_portp->ahciport_mutex); 1520 return (SATA_TRAN_PORT_ERROR); 1521 } 1522 } 1523 } 1524 1525 if (AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_FAILED || 1526 AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_SHUTDOWN|| 1527 AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_PWROFF) { 1528 /* 1529 * In case the target driver would send the packet before 1530 * sata framework can have the opportunity to process those 1531 * event reports. 1532 */ 1533 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1534 spkt->satapkt_device.satadev_state = 1535 ahci_portp->ahciport_port_state; 1536 ahci_update_sata_registers(ahci_ctlp, port, 1537 &spkt->satapkt_device); 1538 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1539 "ahci_tran_start returning PORT_ERROR while " 1540 "port in FAILED/SHUTDOWN/PWROFF state: " 1541 "port: %s", portstr); 1542 mutex_exit(&ahci_portp->ahciport_mutex); 1543 return (SATA_TRAN_PORT_ERROR); 1544 } 1545 1546 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) == SATA_DTYPE_NONE) { 1547 /* 1548 * ahci_intr_phyrdy_change() may have rendered it to 1549 * SATA_DTYPE_NONE. 1550 */ 1551 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1552 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1553 spkt->satapkt_device.satadev_state = 1554 ahci_portp->ahciport_port_state; 1555 ahci_update_sata_registers(ahci_ctlp, port, 1556 &spkt->satapkt_device); 1557 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1558 "ahci_tran_start returning PORT_ERROR while " 1559 "no device attached: port: %s", portstr); 1560 mutex_exit(&ahci_portp->ahciport_mutex); 1561 return (SATA_TRAN_PORT_ERROR); 1562 } 1563 1564 /* R/W PMULT command will occupy the whole HBA port */ 1565 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) { 1566 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1567 "ahci_tran_start returning BUSY while " 1568 "executing READ/WRITE PORT-MULT command: " 1569 "port: %s", portstr); 1570 spkt->satapkt_reason = SATA_PKT_BUSY; 1571 mutex_exit(&ahci_portp->ahciport_mutex); 1572 return (SATA_TRAN_BUSY); 1573 } 1574 1575 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) { 1576 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1577 "ahci_tran_start returning BUSY while " 1578 "hot-plug in progress: port: %s", portstr); 1579 spkt->satapkt_reason = SATA_PKT_BUSY; 1580 mutex_exit(&ahci_portp->ahciport_mutex); 1581 return (SATA_TRAN_BUSY); 1582 } 1583 1584 /* 1585 * SATA HBA driver should remember that a device was reset and it 1586 * is supposed to reject any packets which do not specify either 1587 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1588 * 1589 * This is to prevent a race condition when a device was arbitrarily 1590 * reset by the HBA driver (and lost it's setting) and a target 1591 * driver sending some commands to a device before the sata framework 1592 * has a chance to restore the device setting (such as cache enable/ 1593 * disable or other resettable stuff). 1594 */ 1595 /* 1596 * It is unnecessary to use specific flags to indicate 1597 * reset_in_progress for a pmport. While mopping, all command will be 1598 * mopped so that the entire HBA port is being dealt as a single 1599 * object. 1600 */ 1601 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1602 ahci_portp->ahciport_reset_in_progress = 0; 1603 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1604 "ahci_tran_start [CLEAR] the " 1605 "reset_in_progress for port: %d", port); 1606 } 1607 1608 if (ahci_portp->ahciport_reset_in_progress && 1609 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1610 ! ddi_in_panic()) { 1611 spkt->satapkt_reason = SATA_PKT_BUSY; 1612 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1613 "ahci_tran_start returning BUSY while " 1614 "reset in progress: port: %d", port); 1615 mutex_exit(&ahci_portp->ahciport_mutex); 1616 return (SATA_TRAN_BUSY); 1617 } 1618 1619 #ifdef AHCI_DEBUG 1620 if (spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset) { 1621 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1622 "ahci_tran_start: packet 0x%p [PASSTHRU] at port %d", 1623 spkt, port); 1624 } 1625 #endif 1626 1627 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1628 spkt->satapkt_reason = SATA_PKT_BUSY; 1629 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1630 "ahci_tran_start returning BUSY while " 1631 "mopping in progress: port: %d", port); 1632 mutex_exit(&ahci_portp->ahciport_mutex); 1633 return (SATA_TRAN_BUSY); 1634 } 1635 1636 if (spkt->satapkt_op_mode & 1637 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1638 /* 1639 * If a SYNC command to be executed in interrupt context, 1640 * bounce it back to sata module. 1641 */ 1642 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) && 1643 servicing_interrupt()) { 1644 spkt->satapkt_reason = SATA_PKT_BUSY; 1645 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1646 "ahci_tran_start returning BUSY while " 1647 "sending SYNC mode under interrupt context: " 1648 "port : %d", port); 1649 mutex_exit(&ahci_portp->ahciport_mutex); 1650 return (SATA_TRAN_BUSY); 1651 } 1652 1653 /* We need to do the sync start now */ 1654 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr, 1655 spkt) == AHCI_FAILURE) { 1656 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1657 "return QUEUE_FULL: port %d", port); 1658 mutex_exit(&ahci_portp->ahciport_mutex); 1659 return (SATA_TRAN_QUEUE_FULL); 1660 } 1661 } else { 1662 /* Async start, using interrupt */ 1663 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, &addr, spkt) 1664 == AHCI_FAILURE) { 1665 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1666 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1667 "returning QUEUE_FULL: port %d", port); 1668 mutex_exit(&ahci_portp->ahciport_mutex); 1669 return (SATA_TRAN_QUEUE_FULL); 1670 } 1671 } 1672 1673 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1674 "sata tran accepted: port %s", portstr); 1675 1676 mutex_exit(&ahci_portp->ahciport_mutex); 1677 return (SATA_TRAN_ACCEPTED); 1678 } 1679 1680 /* 1681 * SATA_OPMODE_SYNCH flag is set 1682 * 1683 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1684 * without interrupt, otherwise we can still use the interrupt. 1685 * 1686 * WARNING!!! ahciport_mutex should be acquired before the function 1687 * is called. 1688 */ 1689 static int 1690 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1691 ahci_addr_t *addrp, sata_pkt_t *spkt) 1692 { 1693 int pkt_timeout_ticks; 1694 uint32_t timeout_tags; 1695 int rval; 1696 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1697 uint8_t port = addrp->aa_port; 1698 1699 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1700 "port %d:%d spkt 0x%p", port, addrp->aa_pmport, spkt); 1701 1702 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1703 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1704 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1705 addrp, spkt)) == AHCI_FAILURE) { 1706 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1707 return (rval); 1708 } 1709 1710 pkt_timeout_ticks = 1711 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1712 1713 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1714 mutex_exit(&ahci_portp->ahciport_mutex); 1715 1716 /* Simulate the interrupt */ 1717 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1718 1719 drv_usecwait(AHCI_10MS_USECS); 1720 1721 mutex_enter(&ahci_portp->ahciport_mutex); 1722 pkt_timeout_ticks -= AHCI_10MS_TICKS; 1723 if (pkt_timeout_ticks < 0) { 1724 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1725 "port %d satapkt 0x%p timed out\n", 1726 instance, port, (void *)spkt); 1727 timeout_tags = (0x1 << rval); 1728 mutex_exit(&ahci_portp->ahciport_mutex); 1729 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1730 port, timeout_tags); 1731 mutex_enter(&ahci_portp->ahciport_mutex); 1732 } 1733 } 1734 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1735 return (AHCI_SUCCESS); 1736 1737 } else { 1738 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1739 addrp, spkt)) == AHCI_FAILURE) 1740 return (rval); 1741 1742 #if AHCI_DEBUG 1743 /* 1744 * Note that the driver always uses the slot 0 to deliver 1745 * REQUEST SENSE or READ LOG EXT command 1746 */ 1747 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1748 ASSERT(rval == 0); 1749 #endif 1750 1751 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1752 cv_wait(&ahci_portp->ahciport_cv, 1753 &ahci_portp->ahciport_mutex); 1754 1755 return (AHCI_SUCCESS); 1756 } 1757 } 1758 1759 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1760 if (satapkt) { \ 1761 satapkt->satapkt_reason = reason; \ 1762 /* \ 1763 * We set the satapkt_reason in both sync and \ 1764 * non-sync cases. \ 1765 */ \ 1766 } \ 1767 if (satapkt && \ 1768 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1769 satapkt->satapkt_comp) { \ 1770 mutex_exit(&ahci_portp->ahciport_mutex); \ 1771 (*satapkt->satapkt_comp)(satapkt); \ 1772 mutex_enter(&ahci_portp->ahciport_mutex); \ 1773 } else { \ 1774 if (satapkt && \ 1775 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1776 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1777 cv_broadcast(&ahci_portp->ahciport_cv); \ 1778 } 1779 1780 /* 1781 * Searches for and claims a free command slot. 1782 * 1783 * Returns value: 1784 * 1785 * AHCI_FAILURE returned only if 1786 * 1. No empty slot left 1787 * 2. Non-queued command requested while queued command(s) is outstanding 1788 * 3. Queued command requested while non-queued command(s) is outstanding 1789 * 4. HBA doesn't support multiple-use of command list while already a 1790 * non-queued command is oustanding 1791 * 5. Queued command requested while some queued command(s) has been 1792 * outstanding on a different port multiplier port. (AHCI spec 1.2, 1793 * 9.1.2) 1794 * 1795 * claimed slot number returned if succeeded 1796 * 1797 * NOTE: it will always return slot 0 for following commands to simplify the 1798 * algorithm. 1799 * 1. REQUEST SENSE or READ LOG EXT command during error recovery process 1800 * 2. READ/WRITE PORTMULT command 1801 * 1802 * WARNING!!! ahciport_mutex should be acquired before the function 1803 * is called. 1804 */ 1805 static int 1806 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1807 ahci_addr_t *addrp, int command_type) 1808 { 1809 uint32_t port_cmd_issue; 1810 uint32_t free_slots; 1811 int slot; 1812 1813 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1814 "ahciport_pending_tags = 0x%x " 1815 "ahciport_pending_ncq_tags = 0x%x", 1816 ahci_portp->ahciport_pending_tags, 1817 ahci_portp->ahciport_pending_ncq_tags); 1818 1819 /* 1820 * According to the AHCI spec, system software is responsible to 1821 * ensure that queued and non-queued commands are not mixed in 1822 * the command list. 1823 */ 1824 if (command_type == AHCI_NON_NCQ_CMD) { 1825 /* Non-NCQ command request */ 1826 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1827 AHCIDBG(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1828 "ahci_claim_free_slot: there is still pending " 1829 "queued command(s) in the command list, " 1830 "so no available slot for the non-queued " 1831 "command", NULL); 1832 return (AHCI_FAILURE); 1833 } 1834 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) { 1835 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 1836 "ahci_claim_free_slot: there is still pending " 1837 "read/write port-mult command(s) in command list, " 1838 "so no available slot for the non-queued command", 1839 NULL); 1840 return (AHCI_FAILURE); 1841 } 1842 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1843 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1844 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1845 "ahci_claim_free_slot: HBA cannot support multiple-" 1846 "use of the command list for non-queued commands", 1847 NULL); 1848 return (AHCI_FAILURE); 1849 } 1850 free_slots = (~ahci_portp->ahciport_pending_tags) & 1851 AHCI_SLOT_MASK(ahci_ctlp); 1852 } else if (command_type == AHCI_NCQ_CMD) { 1853 /* NCQ command request */ 1854 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1855 AHCIDBG(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1856 "ahci_claim_free_slot: there is still pending " 1857 "non-queued command(s) in the command list, " 1858 "so no available slot for the queued command", 1859 NULL); 1860 return (AHCI_FAILURE); 1861 } 1862 1863 /* 1864 * NCQ commands cannot be sent to different port multiplier 1865 * ports in Command-Based Switching mode 1866 */ 1867 /* 1868 * NOTE: In Command-Based Switching mode, AHCI controller 1869 * usually reports a 'Handshake Error' when multiple NCQ 1870 * commands are outstanding simultaneously. 1871 */ 1872 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_PMULT) { 1873 ASSERT(ahci_portp->ahciport_pmult_info != NULL); 1874 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_FBSS) && 1875 NCQ_CMD_IN_PROGRESS(ahci_portp) && 1876 AHCIPORT_NCQ_PMPORT(ahci_portp) != 1877 addrp->aa_pmport) { 1878 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1879 "ahci_claim_free_slot: there is still " 1880 "pending queued command(s) in the " 1881 "command list for another Port Multiplier " 1882 "port, so no available slot.", NULL); 1883 return (AHCI_FAILURE); 1884 } 1885 } 1886 1887 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1888 AHCI_NCQ_SLOT_MASK(ahci_portp); 1889 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1890 /* Error retrieval command request */ 1891 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 1892 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1893 "SENSE or READ LOG EXT command", NULL); 1894 slot = 0; 1895 goto out; 1896 } else if (command_type == AHCI_RDWR_PMULT_CMD) { 1897 /* 1898 * An extra check on PxCI. Sometimes PxCI bits may not be 1899 * cleared during hot-plug or error recovery process. 1900 */ 1901 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1902 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, addrp->aa_port)); 1903 1904 if (port_cmd_issue != 0) { 1905 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 1906 "ahci_claim_free_slot: there is still pending " 1907 "command(s) in command list (0x%x/0x%x, PxCI %x)," 1908 "so no available slot for R/W PMULT command.", 1909 NON_NCQ_CMD_IN_PROGRESS(ahci_portp), 1910 NCQ_CMD_IN_PROGRESS(ahci_portp), 1911 port_cmd_issue); 1912 return (AHCI_FAILURE); 1913 } 1914 1915 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 1916 "ahci_claim_free_slot: slot 0 is allocated for " 1917 "READ/WRITE PORTMULT command", NULL); 1918 slot = 0; 1919 goto out; 1920 } 1921 1922 slot = ddi_ffs(free_slots) - 1; 1923 if (slot == -1) { 1924 AHCIDBG(AHCIDBG_VERBOSE, ahci_ctlp, 1925 "ahci_claim_free_slot: no empty slots", NULL); 1926 return (AHCI_FAILURE); 1927 } 1928 1929 /* 1930 * According to the AHCI spec, to allow a simple mechanism for the 1931 * HBA to map command list slots to queue entries, software must 1932 * match the tag number it uses to the slot it is placing the command 1933 * in. For example, if a queued command is placed in slot 5, the tag 1934 * for that command must be 5. 1935 */ 1936 if (command_type == AHCI_NCQ_CMD) { 1937 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1938 if (AHCI_ADDR_IS_PMPORT(addrp)) { 1939 ASSERT(ahci_portp->ahciport_pmult_info != NULL); 1940 AHCIPORT_NCQ_PMPORT(ahci_portp) = addrp->aa_pmport; 1941 } 1942 } 1943 1944 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1945 1946 out: 1947 AHCIDBG(AHCIDBG_VERBOSE, ahci_ctlp, 1948 "ahci_claim_free_slot: found slot: 0x%x", slot); 1949 1950 return (slot); 1951 } 1952 1953 /* 1954 * Builds the Command Table for the sata packet and delivers it to controller. 1955 * 1956 * Returns: 1957 * slot number if we can obtain a slot successfully 1958 * otherwise, return AHCI_FAILURE 1959 * 1960 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1961 */ 1962 static int 1963 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1964 ahci_addr_t *addrp, sata_pkt_t *spkt) 1965 { 1966 int cmd_slot; 1967 sata_cmd_t *scmd; 1968 ahci_fis_h2d_register_t *h2d_register_fisp; 1969 ahci_cmd_table_t *cmd_table; 1970 ahci_cmd_header_t *cmd_header; 1971 int ncookies; 1972 int i; 1973 int command_type = AHCI_NON_NCQ_CMD; 1974 int ncq_qdepth; 1975 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1976 uint8_t port, pmport; 1977 #if AHCI_DEBUG 1978 uint32_t *ptr; 1979 uint8_t *ptr2; 1980 #endif 1981 1982 port = addrp->aa_port; 1983 pmport = addrp->aa_pmport; 1984 1985 spkt->satapkt_reason = SATA_PKT_BUSY; 1986 1987 scmd = &spkt->satapkt_cmd; 1988 1989 /* Check if the command is a NCQ command */ 1990 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1991 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1992 command_type = AHCI_NCQ_CMD; 1993 1994 /* 1995 * When NCQ is support, system software must determine the 1996 * maximum tag allowed by the device and the HBA, and it 1997 * must use a value not beyond of the lower bound of the two. 1998 * 1999 * Sata module is going to calculate the qdepth and send 2000 * down to HBA driver via sata_cmd. 2001 */ 2002 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 2003 2004 /* 2005 * At the moment, the driver doesn't support the dynamic 2006 * setting of the maximum ncq depth, and the value can be 2007 * set either during the attach or after hot-plug insertion. 2008 */ 2009 if (ahci_portp->ahciport_max_ncq_tags == 0) { 2010 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 2011 AHCIDBG(AHCIDBG_NCQ, ahci_ctlp, 2012 "ahci_deliver_satapkt: port %d the max tags for " 2013 "NCQ command is %d", port, ncq_qdepth); 2014 } else { 2015 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 2016 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 2017 " port %d the max tag for NCQ command is " 2018 "requested to change from %d to %d, at the" 2019 " moment the driver doesn't support the " 2020 "dynamic change so it's going to " 2021 "still use the previous tag value", 2022 instance, port, 2023 ahci_portp->ahciport_max_ncq_tags, 2024 ncq_qdepth); 2025 } 2026 } 2027 } 2028 2029 /* Check if the command is an error retrieval command */ 2030 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 2031 command_type = AHCI_ERR_RETRI_CMD; 2032 2033 /* Check if the command is an read/write pmult command */ 2034 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) 2035 command_type = AHCI_RDWR_PMULT_CMD; 2036 2037 /* Check if there is an empty command slot */ 2038 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, 2039 addrp, command_type); 2040 if (cmd_slot == AHCI_FAILURE) { 2041 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "no free command slot", NULL); 2042 return (AHCI_FAILURE); 2043 } 2044 2045 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 2046 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 2047 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 2048 cmd_slot, port, (void *)spkt); 2049 2050 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 2051 bzero((void *)cmd_table, ahci_cmd_table_size); 2052 2053 /* For data transfer operations, it is the H2D Register FIS */ 2054 h2d_register_fisp = 2055 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2056 2057 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2058 2059 /* 2060 * PMP field only make sense when target is a port multiplier or a 2061 * device behind a port multiplier. Otherwise should set it to 0. 2062 */ 2063 if (AHCI_ADDR_IS_PMULT(addrp) || AHCI_ADDR_IS_PMPORT(addrp)) 2064 SET_FIS_PMP(h2d_register_fisp, pmport); 2065 2066 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 2067 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 2068 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 2069 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 2070 2071 switch (scmd->satacmd_addr_type) { 2072 2073 case 0: 2074 /* 2075 * satacmd_addr_type will be 0 for the commands below: 2076 * ATAPI command 2077 * SATAC_IDLE_IM 2078 * SATAC_STANDBY_IM 2079 * SATAC_DOWNLOAD_MICROCODE 2080 * SATAC_FLUSH_CACHE 2081 * SATAC_SET_FEATURES 2082 * SATAC_SMART 2083 * SATAC_ID_PACKET_DEVICE 2084 * SATAC_ID_DEVICE 2085 * SATAC_READ_PORTMULT 2086 * SATAC_WRITE_PORTMULT 2087 */ 2088 /* FALLTHRU */ 2089 2090 case ATA_ADDR_LBA: 2091 /* FALLTHRU */ 2092 2093 case ATA_ADDR_LBA28: 2094 /* LBA[7:0] */ 2095 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 2096 2097 /* LBA[15:8] */ 2098 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 2099 2100 /* LBA[23:16] */ 2101 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 2102 2103 /* LBA [27:24] (also called dev_head) */ 2104 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 2105 2106 break; 2107 2108 case ATA_ADDR_LBA48: 2109 /* LBA[7:0] */ 2110 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 2111 2112 /* LBA[15:8] */ 2113 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 2114 2115 /* LBA[23:16] */ 2116 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 2117 2118 /* LBA [31:24] */ 2119 SET_FIS_SECTOR_EXP(h2d_register_fisp, 2120 scmd->satacmd_lba_low_msb); 2121 2122 /* LBA [39:32] */ 2123 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 2124 scmd->satacmd_lba_mid_msb); 2125 2126 /* LBA [47:40] */ 2127 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 2128 scmd->satacmd_lba_high_msb); 2129 2130 /* Set dev_head */ 2131 SET_FIS_DEV_HEAD(h2d_register_fisp, 2132 scmd->satacmd_device_reg); 2133 2134 /* Set the extended sector count and features */ 2135 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 2136 scmd->satacmd_sec_count_msb); 2137 SET_FIS_FEATURES_EXP(h2d_register_fisp, 2138 scmd->satacmd_features_reg_ext); 2139 break; 2140 } 2141 2142 /* 2143 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 2144 * filled into features field, and sector count 8:15 is filled into 2145 * features (exp) field. The hba driver doesn't need to anything 2146 * special with regard to this, since sata framework has already 2147 * done so. 2148 * 2149 * However the driver needs to make sure TAG is filled into sector 2150 * field. 2151 */ 2152 if (command_type == AHCI_NCQ_CMD) { 2153 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 2154 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 2155 } 2156 2157 ncookies = scmd->satacmd_num_dma_cookies; 2158 AHCIDBG(AHCIDBG_PRDT, ahci_ctlp, 2159 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 2160 ncookies, ahci_dma_prdt_number); 2161 2162 ASSERT(ncookies <= ahci_dma_prdt_number); 2163 ahci_portp->ahciport_prd_bytecounts[cmd_slot] = 0; 2164 2165 /* *** now fill the scatter gather list ******* */ 2166 for (i = 0; i < ncookies; i++) { 2167 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 2168 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 2169 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 2170 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 2171 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 2172 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 2173 ahci_portp->ahciport_prd_bytecounts[cmd_slot] += 2174 scmd->satacmd_dma_cookie_list[i].dmac_size; 2175 } 2176 2177 AHCIDBG(AHCIDBG_PRDT, ahci_ctlp, 2178 "ahciport_prd_bytecounts 0x%x for cmd_slot 0x%x", 2179 ahci_portp->ahciport_prd_bytecounts[cmd_slot], cmd_slot); 2180 2181 /* The ACMD field is filled in for ATAPI command */ 2182 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 2183 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 2184 SATA_ATAPI_MAX_CDB_LEN); 2185 } 2186 2187 /* Set Command Header in Command List */ 2188 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 2189 BZERO_DESCR_INFO(cmd_header); 2190 BZERO_PRD_BYTE_COUNT(cmd_header); 2191 2192 /* Set the number of entries in the PRD table */ 2193 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 2194 2195 /* Set the length of the command in the CFIS area */ 2196 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 2197 2198 /* 2199 * PMP field only make sense when target is a port multiplier or a 2200 * device behind a port multiplier. Otherwise should set it to 0. 2201 */ 2202 if (AHCI_ADDR_IS_PMULT(addrp) || AHCI_ADDR_IS_PMPORT(addrp)) 2203 SET_PORT_MULTI_PORT(cmd_header, pmport); 2204 2205 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 2206 "sata_data_direction = 0x%x", 2207 scmd->satacmd_flags.sata_data_direction); 2208 2209 /* Set A bit if it is an ATAPI command */ 2210 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 2211 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 2212 2213 /* Set W bit if data is going to the device */ 2214 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 2215 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 2216 2217 /* 2218 * Set the prefetchable bit - this bit is only valid if the PRDTL 2219 * field is non-zero or the ATAPI 'A' bit is set in the command 2220 * header. This bit cannot be set when using native command 2221 * queuing commands or when using FIS-based switching with a Port 2222 * multiplier. 2223 */ 2224 if (command_type != AHCI_NCQ_CMD) 2225 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 2226 2227 /* 2228 * Now remember the sata packet in ahciport_slot_pkts[]. 2229 * Error retrieval command and r/w port multiplier command will 2230 * be stored specifically for each port. 2231 */ 2232 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 2233 !RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) 2234 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 2235 2236 /* 2237 * We are overloading satapkt_hba_driver_private with 2238 * watched_cycle count. 2239 */ 2240 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 2241 2242 #if AHCI_DEBUG 2243 if (ahci_debug_flags & AHCIDBG_ATACMD && 2244 scmd->satacmd_cmd_reg != SATAC_PACKET || 2245 ahci_debug_flags & AHCIDBG_ATAPICMD && 2246 scmd->satacmd_cmd_reg == SATAC_PACKET) { 2247 2248 /* Dump the command header and table */ 2249 ahci_log(ahci_ctlp, CE_WARN, "\n"); 2250 ahci_log(ahci_ctlp, CE_WARN, "Command header&table for spkt " 2251 "0x%p cmd_reg 0x%x port %d", spkt, 2252 scmd->satacmd_cmd_reg, port); 2253 ptr = (uint32_t *)cmd_header; 2254 ahci_log(ahci_ctlp, CE_WARN, 2255 " Command Header:%8x %8x %8x %8x", 2256 ptr[0], ptr[1], ptr[2], ptr[3]); 2257 2258 /* Dump the H2D register FIS */ 2259 ptr = (uint32_t *)h2d_register_fisp; 2260 ahci_log(ahci_ctlp, CE_WARN, 2261 " Command FIS: %8x %8x %8x %8x", 2262 ptr[0], ptr[1], ptr[2], ptr[3]); 2263 2264 /* Dump the ACMD register FIS */ 2265 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 2266 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 2267 if (ahci_debug_flags & AHCIDBG_ATAPICMD) 2268 ahci_log(ahci_ctlp, CE_WARN, 2269 " ATAPI command: %2x %2x %2x %2x " 2270 "%2x %2x %2x %2x", 2271 ptr2[8 * i], ptr2[8 * i + 1], 2272 ptr2[8 * i + 2], ptr2[8 * i + 3], 2273 ptr2[8 * i + 4], ptr2[8 * i + 5], 2274 ptr2[8 * i + 6], ptr2[8 * i + 7]); 2275 2276 /* Dump the PRDT */ 2277 for (i = 0; i < ncookies; i++) { 2278 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 2279 ahci_log(ahci_ctlp, CE_WARN, 2280 " Cookie %d: %8x %8x %8x %8x", 2281 i, ptr[0], ptr[1], ptr[2], ptr[3]); 2282 } 2283 } 2284 #endif 2285 2286 (void) ddi_dma_sync( 2287 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 2288 0, 2289 ahci_cmd_table_size, 2290 DDI_DMA_SYNC_FORDEV); 2291 2292 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2293 cmd_slot * sizeof (ahci_cmd_header_t), 2294 sizeof (ahci_cmd_header_t), 2295 DDI_DMA_SYNC_FORDEV); 2296 2297 /* Set the corresponding bit in the PxSACT.DS for queued command */ 2298 if (command_type == AHCI_NCQ_CMD) { 2299 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2300 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 2301 (0x1 << cmd_slot)); 2302 } 2303 2304 /* Indicate to the HBA that a command is active. */ 2305 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2306 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2307 (0x1 << cmd_slot)); 2308 2309 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 2310 "exit: port %d", port); 2311 2312 return (cmd_slot); 2313 } 2314 2315 /* 2316 * Called by the sata framework to abort the previously sent packet(s). 2317 * 2318 * Reset device to abort commands. 2319 */ 2320 static int 2321 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 2322 { 2323 ahci_ctl_t *ahci_ctlp; 2324 ahci_port_t *ahci_portp; 2325 uint32_t slot_status = 0; 2326 uint32_t aborted_tags = 0; 2327 uint32_t finished_tags = 0; 2328 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 2329 uint8_t port; 2330 int tmp_slot; 2331 int instance = ddi_get_instance(dip); 2332 2333 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2334 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2335 2336 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 2337 "ahci_tran_abort enter: port %d", port); 2338 2339 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2340 mutex_enter(&ahci_portp->ahciport_mutex); 2341 2342 /* 2343 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2344 * commands are being mopped, therefore there is nothing else to do 2345 */ 2346 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2347 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 2348 "ahci_tran_abort: port %d is in " 2349 "mopping process, so just return directly ", port); 2350 mutex_exit(&ahci_portp->ahciport_mutex); 2351 return (SATA_SUCCESS); 2352 } 2353 2354 /* 2355 * If AHCI_PORT_FLAG_RDWR_PMULT flag is set, it means a R/W PMULT 2356 * command is being executed so no other commands is outstanding, 2357 * nothing to do. 2358 */ 2359 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RDWR_PMULT) { 2360 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 2361 "ahci_tran_abort: port %d is reading/writing " 2362 "port multiplier, so just return directly ", port); 2363 mutex_exit(&ahci_portp->ahciport_mutex); 2364 return (SATA_SUCCESS); 2365 } 2366 2367 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2368 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2369 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2370 /* 2371 * In case the targer driver would send the request before 2372 * sata framework can have the opportunity to process those 2373 * event reports. 2374 */ 2375 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2376 spkt->satapkt_device.satadev_state = 2377 ahci_portp->ahciport_port_state; 2378 ahci_update_sata_registers(ahci_ctlp, port, 2379 &spkt->satapkt_device); 2380 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2381 "ahci_tran_abort returning SATA_FAILURE while " 2382 "port in FAILED/SHUTDOWN/PWROFF state: " 2383 "port: %d", port); 2384 mutex_exit(&ahci_portp->ahciport_mutex); 2385 return (SATA_FAILURE); 2386 } 2387 2388 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2389 /* 2390 * ahci_intr_phyrdy_change() may have rendered it to 2391 * AHCI_PORT_TYPE_NODEV. 2392 */ 2393 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2394 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 2395 spkt->satapkt_device.satadev_state = 2396 ahci_portp->ahciport_port_state; 2397 ahci_update_sata_registers(ahci_ctlp, port, 2398 &spkt->satapkt_device); 2399 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2400 "ahci_tran_abort returning SATA_FAILURE while " 2401 "no device attached: port: %d", port); 2402 mutex_exit(&ahci_portp->ahciport_mutex); 2403 return (SATA_FAILURE); 2404 } 2405 2406 if (flag == SATA_ABORT_ALL_PACKETS) { 2407 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2408 aborted_tags = ahci_portp->ahciport_pending_tags; 2409 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2410 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 2411 2412 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 2413 instance, port); 2414 } else { 2415 aborted_tags = 0xffffffff; 2416 /* 2417 * Aborting one specific packet, first search the 2418 * ahciport_slot_pkts[] list for matching spkt. 2419 */ 2420 for (tmp_slot = 0; 2421 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 2422 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 2423 aborted_tags = (0x1 << tmp_slot); 2424 break; 2425 } 2426 } 2427 2428 if (aborted_tags == 0xffffffff) { 2429 /* request packet is not on the pending list */ 2430 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 2431 "Cannot find the aborting pkt 0x%p on the " 2432 "pending list", (void *)spkt); 2433 ahci_update_sata_registers(ahci_ctlp, port, 2434 &spkt->satapkt_device); 2435 mutex_exit(&ahci_portp->ahciport_mutex); 2436 return (SATA_FAILURE); 2437 } 2438 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 2439 instance, port, (void *)spkt); 2440 } 2441 2442 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2443 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2444 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2445 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2446 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2447 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2448 2449 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2450 ahci_portp->ahciport_mop_in_progress++; 2451 2452 /* 2453 * To abort the packet(s), first we are trying to clear PxCMD.ST 2454 * to stop the port, and if the port can be stopped 2455 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2456 * then we just send back the aborted packet(s) with ABORTED flag 2457 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2458 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2459 * perform a COMRESET. 2460 */ 2461 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2462 ahci_portp, port, NULL, NULL); 2463 2464 /* 2465 * Compute which have finished and which need to be retried. 2466 * 2467 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2468 * minus the slot_status. The aborted_tags has to be deducted by 2469 * finished_tags since we can't possibly abort a tag which had finished 2470 * already. 2471 */ 2472 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2473 finished_tags = ahci_portp->ahciport_pending_tags & 2474 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2475 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2476 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2477 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2478 2479 aborted_tags &= ~finished_tags; 2480 2481 ahci_mop_commands(ahci_ctlp, 2482 ahci_portp, 2483 slot_status, 2484 0, /* failed tags */ 2485 0, /* timeout tags */ 2486 aborted_tags, 2487 0); /* reset tags */ 2488 2489 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2490 mutex_exit(&ahci_portp->ahciport_mutex); 2491 2492 return (SATA_SUCCESS); 2493 } 2494 2495 /* 2496 * Used to do device reset and reject all the pending packets on a device 2497 * during the reset operation. 2498 * 2499 * NOTE: ONLY called by ahci_tran_reset_dport 2500 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2501 */ 2502 static int 2503 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2504 ahci_port_t *ahci_portp, ahci_addr_t *addrp) 2505 { 2506 uint32_t slot_status = 0; 2507 uint32_t reset_tags = 0; 2508 uint32_t finished_tags = 0; 2509 uint8_t port = addrp->aa_port; 2510 sata_device_t sdevice; 2511 int ret; 2512 2513 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 2514 "ahci_reset_device_reject_pkts on port: %d", port); 2515 2516 /* 2517 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2518 * commands are being mopped, therefore there is nothing else to do 2519 */ 2520 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2521 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2522 "ahci_reset_device_reject_pkts: port %d is in " 2523 "mopping process, so return directly ", port); 2524 return (SATA_SUCCESS); 2525 } 2526 2527 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2528 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2529 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2530 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2531 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2532 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2533 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2534 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2535 } 2536 2537 if (ahci_software_reset(ahci_ctlp, ahci_portp, addrp) 2538 != AHCI_SUCCESS) { 2539 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2540 "Try to do a port reset after software " 2541 "reset failed", port); 2542 ret = ahci_port_reset(ahci_ctlp, ahci_portp, addrp); 2543 if (ret != AHCI_SUCCESS) { 2544 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2545 "ahci_reset_device_reject_pkts: port %d " 2546 "failed", port); 2547 return (SATA_FAILURE); 2548 } 2549 } 2550 /* Set the reset in progress flag */ 2551 ahci_portp->ahciport_reset_in_progress = 1; 2552 2553 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2554 ahci_portp->ahciport_mop_in_progress++; 2555 2556 /* Indicate to the framework that a reset has happened */ 2557 bzero((void *)&sdevice, sizeof (sata_device_t)); 2558 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2559 sdevice.satadev_addr.pmport = 0; 2560 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2561 sdevice.satadev_state = SATA_DSTATE_RESET | 2562 SATA_DSTATE_PWR_ACTIVE; 2563 mutex_exit(&ahci_portp->ahciport_mutex); 2564 sata_hba_event_notify( 2565 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2566 &sdevice, 2567 SATA_EVNT_DEVICE_RESET); 2568 mutex_enter(&ahci_portp->ahciport_mutex); 2569 2570 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp, 2571 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port); 2572 2573 /* Next try to mop the pending commands */ 2574 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2575 finished_tags = ahci_portp->ahciport_pending_tags & 2576 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2577 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2578 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2579 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2580 2581 reset_tags &= ~finished_tags; 2582 2583 ahci_mop_commands(ahci_ctlp, 2584 ahci_portp, 2585 slot_status, 2586 0, /* failed tags */ 2587 0, /* timeout tags */ 2588 0, /* aborted tags */ 2589 reset_tags); /* reset tags */ 2590 2591 return (SATA_SUCCESS); 2592 } 2593 2594 /* 2595 * Used to do device reset and reject all the pending packets on a device 2596 * during the reset operation. 2597 * 2598 * NOTE: ONLY called by ahci_tran_reset_dport 2599 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2600 */ 2601 static int 2602 ahci_reset_pmdevice_reject_pkts(ahci_ctl_t *ahci_ctlp, 2603 ahci_port_t *ahci_portp, ahci_addr_t *addrp) 2604 { 2605 uint32_t finished_tags = 0, reset_tags = 0, slot_status = 0; 2606 uint8_t port = addrp->aa_port; 2607 uint8_t pmport = addrp->aa_pmport; 2608 sata_device_t sdevice; 2609 2610 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_PMULT, ahci_ctlp, 2611 "ahci_reset_pmdevice_reject_pkts at port %d:%d", port, pmport); 2612 2613 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2614 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2615 "ahci_reset_pmdevice_reject_pkts: port %d is in " 2616 "mopping process, so return directly ", port); 2617 return (SATA_SUCCESS); 2618 } 2619 2620 /* Checking for outstanding commands */ 2621 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2622 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2623 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2624 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2625 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2626 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2627 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2628 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2629 } 2630 2631 /* Issue SOFTWARE reset command. */ 2632 if (ahci_software_reset(ahci_ctlp, ahci_portp, addrp) 2633 != AHCI_SUCCESS) { 2634 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2635 "Try to do a port reset after software " 2636 "reset failed", port); 2637 return (SATA_FAILURE); 2638 } 2639 2640 /* Set the reset in progress flag */ 2641 ahci_portp->ahciport_reset_in_progress = 1; 2642 2643 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2644 ahci_portp->ahciport_mop_in_progress++; 2645 2646 /* Indicate to the framework that a reset has happened */ 2647 bzero((void *)&sdevice, sizeof (sata_device_t)); 2648 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2649 sdevice.satadev_addr.pmport = pmport; 2650 if (AHCI_ADDR_IS_PMULT(addrp)) 2651 sdevice.satadev_addr.qual = SATA_ADDR_PMULT; 2652 else 2653 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 2654 sdevice.satadev_state = SATA_DSTATE_RESET | 2655 SATA_DSTATE_PWR_ACTIVE; 2656 mutex_exit(&ahci_portp->ahciport_mutex); 2657 sata_hba_event_notify( 2658 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2659 &sdevice, 2660 SATA_EVNT_DEVICE_RESET); 2661 mutex_enter(&ahci_portp->ahciport_mutex); 2662 2663 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp, 2664 "port %d:%d sending event up: SATA_EVNT_DEVICE_RESET", 2665 port, pmport); 2666 2667 /* Next try to mop the pending commands */ 2668 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2669 finished_tags = ahci_portp->ahciport_pending_tags & 2670 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2671 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2672 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2673 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2674 reset_tags &= ~finished_tags; 2675 2676 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp, 2677 "reset_tags = %x, finished_tags = %x, slot_status = %x", 2678 reset_tags, finished_tags, slot_status); 2679 2680 /* 2681 * NOTE: Because PxCI be only erased by unset PxCMD.ST bit, so even we 2682 * try to reset a single device behind a port multiplier will 2683 * terminate all the commands on that HBA port. We need mop these 2684 * commands as well. 2685 */ 2686 ahci_mop_commands(ahci_ctlp, 2687 ahci_portp, 2688 slot_status, 2689 0, /* failed tags */ 2690 0, /* timeout tags */ 2691 0, /* aborted tags */ 2692 reset_tags); /* reset tags */ 2693 2694 return (SATA_SUCCESS); 2695 } 2696 2697 /* 2698 * Used to do port reset and reject all the pending packets on a port during 2699 * the reset operation. 2700 * 2701 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2702 */ 2703 static int 2704 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2705 ahci_port_t *ahci_portp, ahci_addr_t *addrp) 2706 { 2707 uint32_t slot_status = 0; 2708 uint32_t reset_tags = 0; 2709 uint32_t finished_tags = 0; 2710 uint8_t port = addrp->aa_port; 2711 2712 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 2713 "ahci_reset_port_reject_pkts at port: %d", port); 2714 2715 /* 2716 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2717 * commands are being mopped, therefore there is nothing else to do 2718 */ 2719 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2720 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2721 "ahci_reset_port_reject_pkts: port %d is in " 2722 "mopping process, so return directly ", port); 2723 return (SATA_SUCCESS); 2724 } 2725 2726 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2727 ahci_portp->ahciport_mop_in_progress++; 2728 2729 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2730 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2731 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2732 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2733 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2734 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2735 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2736 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2737 } 2738 2739 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2740 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2741 NULL) != AHCI_SUCCESS) { 2742 2743 /* Clear mop flag */ 2744 ahci_portp->ahciport_mop_in_progress--; 2745 if (ahci_portp->ahciport_mop_in_progress == 0) 2746 ahci_portp->ahciport_flags &= 2747 ~AHCI_PORT_FLAG_MOPPING; 2748 return (SATA_FAILURE); 2749 } 2750 2751 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2752 finished_tags = ahci_portp->ahciport_pending_tags & 2753 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2754 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2755 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2756 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2757 2758 reset_tags &= ~finished_tags; 2759 2760 ahci_mop_commands(ahci_ctlp, 2761 ahci_portp, 2762 slot_status, 2763 0, /* failed tags */ 2764 0, /* timeout tags */ 2765 0, /* aborted tags */ 2766 reset_tags); /* reset tags */ 2767 2768 return (SATA_SUCCESS); 2769 } 2770 2771 /* 2772 * Used to do hba reset and reject all the pending packets on all ports 2773 * during the reset operation. 2774 */ 2775 static int 2776 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2777 { 2778 ahci_port_t *ahci_portp; 2779 uint32_t slot_status[AHCI_MAX_PORTS]; 2780 uint32_t reset_tags[AHCI_MAX_PORTS]; 2781 uint32_t finished_tags[AHCI_MAX_PORTS]; 2782 int port; 2783 int ret = SATA_SUCCESS; 2784 2785 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 2786 "ahci_reset_hba_reject_pkts enter", NULL); 2787 2788 bzero(slot_status, sizeof (slot_status)); 2789 bzero(reset_tags, sizeof (reset_tags)); 2790 bzero(finished_tags, sizeof (finished_tags)); 2791 2792 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2793 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2794 continue; 2795 } 2796 2797 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2798 2799 mutex_enter(&ahci_portp->ahciport_mutex); 2800 ahci_portp->ahciport_reset_in_progress = 1; 2801 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2802 slot_status[port] = ddi_get32( 2803 ahci_ctlp->ahcictl_ahci_acc_handle, 2804 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2805 reset_tags[port] = slot_status[port] & 2806 AHCI_SLOT_MASK(ahci_ctlp); 2807 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 2808 "port %d: reset_tags = 0x%x pending_tags = 0x%x", 2809 port, reset_tags[port], 2810 ahci_portp->ahciport_pending_tags); 2811 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2812 slot_status[port] = ddi_get32( 2813 ahci_ctlp->ahcictl_ahci_acc_handle, 2814 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2815 reset_tags[port] = slot_status[port] & 2816 AHCI_NCQ_SLOT_MASK(ahci_portp); 2817 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 2818 "port %d: reset_tags = 0x%x pending_tags = 0x%x", 2819 port, reset_tags[port], 2820 ahci_portp->ahciport_pending_tags); 2821 } 2822 mutex_exit(&ahci_portp->ahciport_mutex); 2823 } 2824 2825 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2826 ret = SATA_FAILURE; 2827 } 2828 2829 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2830 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2831 continue; 2832 } 2833 2834 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2835 2836 mutex_enter(&ahci_portp->ahciport_mutex); 2837 /* 2838 * To prevent recursive enter to ahci_mop_commands, we need 2839 * check AHCI_PORT_FLAG_MOPPING flag. 2840 */ 2841 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2842 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2843 "ahci_reset_hba_reject_pkts: port %d is in " 2844 "mopping process, so return directly ", port); 2845 mutex_exit(&ahci_portp->ahciport_mutex); 2846 continue; 2847 } 2848 2849 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2850 ahci_portp->ahciport_mop_in_progress++; 2851 2852 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2853 finished_tags[port] = 2854 ahci_portp->ahciport_pending_tags & 2855 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2856 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2857 finished_tags[port] = 2858 ahci_portp->ahciport_pending_ncq_tags & 2859 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2860 2861 reset_tags[port] &= ~finished_tags[port]; 2862 2863 ahci_mop_commands(ahci_ctlp, 2864 ahci_portp, 2865 slot_status[port], 2866 0, /* failed tags */ 2867 0, /* timeout tags */ 2868 0, /* aborted tags */ 2869 reset_tags[port]); /* reset tags */ 2870 mutex_exit(&ahci_portp->ahciport_mutex); 2871 } 2872 out: 2873 return (ret); 2874 } 2875 2876 /* 2877 * Called by sata framework to reset a port(s) or device. 2878 */ 2879 static int 2880 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2881 { 2882 ahci_ctl_t *ahci_ctlp; 2883 ahci_port_t *ahci_portp; 2884 ahci_addr_t addr; 2885 uint8_t cport = sd->satadev_addr.cport; 2886 uint8_t pmport = sd->satadev_addr.pmport; 2887 uint8_t port; 2888 int ret = SATA_SUCCESS; 2889 int instance = ddi_get_instance(dip); 2890 2891 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2892 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2893 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2894 2895 ahci_get_ahci_addr(ahci_ctlp, sd, &addr); 2896 2897 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 2898 "ahci_tran_reset_dport enter: cport %d", cport); 2899 2900 switch (sd->satadev_addr.qual) { 2901 case SATA_ADDR_PMPORT: 2902 /* 2903 * If we want to issue a COMRESET on a pmport, we need to 2904 * reject the outstanding commands on that pmport. According 2905 * to AHCI spec, PxCI register could only be cleared by 2906 * clearing PxCMD.ST, which will halt the controller port - as 2907 * well as other pmports. 2908 * 2909 * Therefore we directly reset the controller port for 2910 * simplicity. ahci_tran_probe_port() will handle reset stuff 2911 * like initializing the given pmport. 2912 */ 2913 /* FALLTHRU */ 2914 case SATA_ADDR_CPORT: 2915 /* Port reset */ 2916 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2917 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport " 2918 "port %d reset port", instance, port); 2919 2920 mutex_enter(&ahci_portp->ahciport_mutex); 2921 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, &addr); 2922 mutex_exit(&ahci_portp->ahciport_mutex); 2923 2924 break; 2925 2926 case SATA_ADDR_DPMPORT: 2927 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport " 2928 "port %d:%d reset device", instance, port, pmport); 2929 /* FALLTHRU */ 2930 case SATA_ADDR_DCPORT: 2931 /* Device reset */ 2932 if (sd->satadev_addr.qual == SATA_ADDR_DCPORT) 2933 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport " 2934 "port %d reset device", instance, port); 2935 2936 mutex_enter(&ahci_portp->ahciport_mutex); 2937 /* 2938 * software reset request must be sent to SATA_PMULT_HOSTPORT 2939 * if target is a port multiplier: 2940 */ 2941 if (sd->satadev_addr.qual == SATA_ADDR_DCPORT && 2942 ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) 2943 AHCI_ADDR_SET_PMULT(&addr, port); 2944 2945 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2946 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2947 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2948 /* 2949 * In case the targer driver would send the request 2950 * before sata framework can have the opportunity to 2951 * process those event reports. 2952 */ 2953 sd->satadev_state = ahci_portp->ahciport_port_state; 2954 ahci_update_sata_registers(ahci_ctlp, port, sd); 2955 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2956 "ahci_tran_reset_dport returning SATA_FAILURE " 2957 "while port in FAILED/SHUTDOWN/PWROFF state: " 2958 "port: %d", port); 2959 mutex_exit(&ahci_portp->ahciport_mutex); 2960 ret = SATA_FAILURE; 2961 break; 2962 } 2963 2964 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) == 2965 SATA_DTYPE_NONE) { 2966 /* 2967 * ahci_intr_phyrdy_change() may have rendered it to 2968 * AHCI_PORT_TYPE_NODEV. 2969 */ 2970 sd->satadev_type = SATA_DTYPE_NONE; 2971 sd->satadev_state = AHCIPORT_GET_STATE(ahci_portp, 2972 &addr); 2973 ahci_update_sata_registers(ahci_ctlp, port, sd); 2974 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 2975 "ahci_tran_reset_dport returning SATA_FAILURE " 2976 "while no device attached: port: %d", port); 2977 mutex_exit(&ahci_portp->ahciport_mutex); 2978 ret = SATA_FAILURE; 2979 break; 2980 } 2981 2982 if (AHCI_ADDR_IS_PORT(&addr)) { 2983 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2984 ahci_portp, &addr); 2985 } else { 2986 ret = ahci_reset_pmdevice_reject_pkts(ahci_ctlp, 2987 ahci_portp, &addr); 2988 } 2989 2990 mutex_exit(&ahci_portp->ahciport_mutex); 2991 break; 2992 2993 case SATA_ADDR_CNTRL: 2994 /* Reset the whole controller */ 2995 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport " 2996 "reset the whole hba", instance); 2997 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2998 break; 2999 3000 default: 3001 ret = SATA_FAILURE; 3002 } 3003 3004 return (ret); 3005 } 3006 3007 /* 3008 * Called by sata framework to activate a port as part of hotplug. 3009 * (cfgadm -c connect satax/y) 3010 * Support port multiplier. 3011 */ 3012 static int 3013 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 3014 { 3015 ahci_ctl_t *ahci_ctlp; 3016 ahci_port_t *ahci_portp; 3017 ahci_addr_t addr; 3018 uint8_t cport = satadev->satadev_addr.cport; 3019 uint8_t pmport = satadev->satadev_addr.pmport; 3020 uint8_t port; 3021 int instance = ddi_get_instance(dip); 3022 3023 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 3024 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 3025 3026 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 3027 "ahci_tran_hotplug_port_activate enter: cport %d", cport); 3028 3029 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3030 3031 mutex_enter(&ahci_portp->ahciport_mutex); 3032 ahci_get_ahci_addr(ahci_ctlp, satadev, &addr); 3033 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMPORT(&addr)); 3034 3035 if (AHCI_ADDR_IS_PORT(&addr)) { 3036 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", 3037 instance, port); 3038 3039 /* Enable the interrupts on the port */ 3040 ahci_enable_port_intrs(ahci_ctlp, port); 3041 3042 /* 3043 * Reset the port so that the PHY communication would be 3044 * re-established. But this reset is an internal operation 3045 * and the sata module doesn't need to know about it. 3046 * Moreover, the port with a device attached will be started 3047 * too. 3048 */ 3049 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 3050 ahci_portp, port, 3051 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 3052 NULL); 3053 3054 /* 3055 * Need to check the link status and device status of the port 3056 * and consider raising power if the port was in D3 state 3057 */ 3058 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 3059 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 3060 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 3061 } else if (AHCI_ADDR_IS_PMPORT(&addr)) { 3062 cmn_err(CE_NOTE, "!ahci%d: ahci port %d:%d is activated", 3063 instance, port, pmport); 3064 /* AHCI_ADDR_PMPORT */ 3065 AHCIPORT_PMSTATE(ahci_portp, &addr) |= SATA_PSTATE_PWRON; 3066 AHCIPORT_PMSTATE(ahci_portp, &addr) &= 3067 ~(SATA_PSTATE_PWROFF|SATA_PSTATE_SHUTDOWN); 3068 } 3069 3070 satadev->satadev_state = ahci_portp->ahciport_port_state; 3071 3072 ahci_update_sata_registers(ahci_ctlp, port, satadev); 3073 3074 mutex_exit(&ahci_portp->ahciport_mutex); 3075 return (SATA_SUCCESS); 3076 } 3077 3078 /* 3079 * Called by sata framework to deactivate a port as part of hotplug. 3080 * (cfgadm -c disconnect satax/y) 3081 * Support port multiplier. 3082 */ 3083 static int 3084 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 3085 { 3086 ahci_ctl_t *ahci_ctlp; 3087 ahci_port_t *ahci_portp; 3088 ahci_addr_t addr; 3089 uint8_t cport = satadev->satadev_addr.cport; 3090 uint8_t pmport = satadev->satadev_addr.pmport; 3091 uint8_t port; 3092 uint32_t port_scontrol; 3093 int instance = ddi_get_instance(dip); 3094 3095 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 3096 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 3097 3098 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 3099 "ahci_tran_hotplug_port_deactivate enter: cport %d", cport); 3100 3101 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3102 mutex_enter(&ahci_portp->ahciport_mutex); 3103 ahci_get_ahci_addr(ahci_ctlp, satadev, &addr); 3104 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMPORT(&addr)); 3105 3106 if (AHCI_ADDR_IS_PORT(&addr)) { 3107 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 3108 instance, port); 3109 3110 /* Disable the interrupts on the port */ 3111 ahci_disable_port_intrs(ahci_ctlp, port); 3112 3113 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 3114 3115 /* First to abort all the pending commands */ 3116 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 3117 3118 /* Then stop the port */ 3119 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 3120 ahci_portp, port); 3121 } 3122 3123 /* Next put the PHY offline */ 3124 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3125 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3126 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 3127 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, (uint32_t *) 3128 AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3129 } else if (AHCI_ADDR_IS_PMPORT(&addr)) { 3130 cmn_err(CE_NOTE, "!ahci%d: ahci port %d:%d is deactivated", 3131 instance, port, pmport); 3132 3133 ahci_disable_port_intrs(ahci_ctlp, port); 3134 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) 3135 != SATA_DTYPE_NONE) 3136 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 3137 3138 /* Re-enable the interrupts for the other pmports */ 3139 ahci_enable_port_intrs(ahci_ctlp, port); 3140 } 3141 3142 /* Update port state */ 3143 AHCIPORT_SET_STATE(ahci_portp, &addr, SATA_PSTATE_SHUTDOWN); 3144 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 3145 3146 ahci_update_sata_registers(ahci_ctlp, port, satadev); 3147 3148 mutex_exit(&ahci_portp->ahciport_mutex); 3149 return (SATA_SUCCESS); 3150 } 3151 3152 /* 3153 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 3154 * when a device is unplugged or a port is deactivated. 3155 * 3156 * WARNING!!! ahciport_mutex should be acquired before the function is called. 3157 */ 3158 static void 3159 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 3160 ahci_port_t *ahci_portp, uint8_t port) 3161 { 3162 uint32_t slot_status = 0; 3163 uint32_t abort_tags = 0; 3164 3165 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 3166 "ahci_reject_all_abort_pkts at port: %d", port); 3167 3168 /* Read/write port multiplier command takes highest priority */ 3169 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) { 3170 slot_status = 0x1; 3171 abort_tags = 0x1; 3172 goto out; 3173 } 3174 3175 /* 3176 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 3177 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 3178 * to get the error data, if yes when the device is removed, the 3179 * command needs to be aborted too. 3180 */ 3181 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 3182 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 3183 slot_status = 0x1; 3184 abort_tags = 0x1; 3185 goto out; 3186 } else { 3187 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 3188 "ahci_reject_all_abort_pkts return directly " 3189 "port %d no needs to reject any outstanding " 3190 "commands", port); 3191 return; 3192 } 3193 } 3194 3195 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 3196 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3197 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3198 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 3199 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 3200 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3201 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 3202 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 3203 } 3204 3205 out: 3206 /* No need to do mop when there is no outstanding commands */ 3207 if (slot_status != 0) { 3208 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 3209 ahci_portp->ahciport_mop_in_progress++; 3210 3211 ahci_mop_commands(ahci_ctlp, 3212 ahci_portp, 3213 slot_status, 3214 0, /* failed tags */ 3215 0, /* timeout tags */ 3216 abort_tags, /* aborting tags */ 3217 0); /* reset tags */ 3218 } 3219 } 3220 3221 #if defined(__lock_lint) 3222 static int 3223 ahci_selftest(dev_info_t *dip, sata_device_t *device) 3224 { 3225 return (SATA_SUCCESS); 3226 } 3227 #endif 3228 3229 /* 3230 * Allocate the ports structure, only called by ahci_attach 3231 */ 3232 static int 3233 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 3234 { 3235 int port, cport = 0; 3236 3237 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3238 "ahci_alloc_ports_state enter", NULL); 3239 3240 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3241 3242 /* Allocate structures only for the implemented ports */ 3243 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3244 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3245 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3246 "hba port %d not implemented", port); 3247 continue; 3248 } 3249 3250 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 3251 ahci_ctlp->ahcictl_port_to_cport[port] = 3252 (uint8_t)cport++; 3253 3254 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 3255 goto err_out; 3256 } 3257 } 3258 3259 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3260 return (AHCI_SUCCESS); 3261 3262 err_out: 3263 for (port--; port >= 0; port--) { 3264 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3265 ahci_dealloc_port_state(ahci_ctlp, port); 3266 } 3267 } 3268 3269 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3270 return (AHCI_FAILURE); 3271 } 3272 3273 /* 3274 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 3275 */ 3276 static void 3277 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 3278 { 3279 int port; 3280 3281 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3282 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3283 /* if this port is implemented by the HBA */ 3284 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 3285 ahci_dealloc_port_state(ahci_ctlp, port); 3286 } 3287 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3288 } 3289 3290 /* 3291 * Drain the taskq. 3292 */ 3293 static void 3294 ahci_drain_ports_taskq(ahci_ctl_t *ahci_ctlp) 3295 { 3296 ahci_port_t *ahci_portp; 3297 int port; 3298 3299 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3300 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3301 continue; 3302 } 3303 3304 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3305 3306 mutex_enter(&ahci_portp->ahciport_mutex); 3307 ddi_taskq_wait(ahci_portp->ahciport_event_taskq); 3308 mutex_exit(&ahci_portp->ahciport_mutex); 3309 } 3310 } 3311 3312 /* 3313 * Initialize the controller and all ports. And then try to start the ports 3314 * if there are devices attached. 3315 * 3316 * This routine can be called from three seperate cases: DDI_ATTACH, 3317 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 3318 * other two cases; device signature probing are attempted only during 3319 * DDI_ATTACH case. 3320 * 3321 * WARNING!!! Disable the whole controller's interrupts before calling and 3322 * the interrupts will be enabled upon successfully return. 3323 */ 3324 static int 3325 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 3326 { 3327 ahci_port_t *ahci_portp; 3328 ahci_addr_t addr; 3329 uint32_t ghc_control; 3330 int port; 3331 3332 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3333 "ahci_initialize_controller enter", NULL); 3334 3335 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3336 3337 /* 3338 * Indicate that system software is AHCI aware by setting 3339 * GHC.AE to 1 3340 */ 3341 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3342 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3343 3344 ghc_control |= AHCI_HBA_GHC_AE; 3345 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3346 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 3347 ghc_control); 3348 3349 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3350 3351 /* Initialize the implemented ports and structures */ 3352 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3353 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3354 continue; 3355 } 3356 3357 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3358 mutex_enter(&ahci_portp->ahciport_mutex); 3359 3360 /* 3361 * Ensure that the controller is not in the running state 3362 * by checking every implemented port's PxCMD register 3363 */ 3364 AHCI_ADDR_SET_PORT(&addr, (uint8_t)port); 3365 3366 if (ahci_initialize_port(ahci_ctlp, ahci_portp, &addr) 3367 != AHCI_SUCCESS) { 3368 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 3369 "ahci_initialize_controller: failed to " 3370 "initialize port %d", port); 3371 /* 3372 * Set the port state to SATA_PSTATE_FAILED if 3373 * failed to initialize it. 3374 */ 3375 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 3376 } 3377 3378 mutex_exit(&ahci_portp->ahciport_mutex); 3379 } 3380 3381 /* Enable the whole controller interrupts */ 3382 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3383 ahci_enable_all_intrs(ahci_ctlp); 3384 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3385 3386 return (AHCI_SUCCESS); 3387 } 3388 3389 /* 3390 * Reverse of ahci_initialize_controller() 3391 * 3392 * We only need to stop the ports and disable the interrupt. 3393 */ 3394 static void 3395 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 3396 { 3397 ahci_port_t *ahci_portp; 3398 int port; 3399 3400 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3401 "ahci_uninitialize_controller enter", NULL); 3402 3403 /* disable all the interrupts. */ 3404 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3405 ahci_disable_all_intrs(ahci_ctlp); 3406 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3407 3408 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3409 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3410 continue; 3411 } 3412 3413 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3414 3415 /* Stop the port by clearing PxCMD.ST */ 3416 mutex_enter(&ahci_portp->ahciport_mutex); 3417 3418 /* 3419 * Here we must disable the port interrupt because 3420 * ahci_disable_all_intrs only clear GHC.IE, and IS 3421 * register will be still set if PxIE is enabled. 3422 * When ahci shares one IRQ with other drivers, the 3423 * intr handler may claim the intr mistakenly. 3424 */ 3425 ahci_disable_port_intrs(ahci_ctlp, port); 3426 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 3427 ahci_portp, port); 3428 mutex_exit(&ahci_portp->ahciport_mutex); 3429 } 3430 } 3431 3432 /* 3433 * ahci_alloc_pmult() 3434 * 1. Setting HBA port registers which are necessary for a port multiplier. 3435 * (Set PxCMD.PMA while PxCMD.ST is '0') 3436 * 2. Allocate ahci_pmult_info structure. 3437 * 3438 * NOTE: Must stop port before the function is called. 3439 * WARNING!!! ahciport_mutex should be acquired before the function is 3440 * called. 3441 */ 3442 static void 3443 ahci_alloc_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3444 { 3445 uint32_t port_cmd_status; 3446 uint8_t port = ahci_portp->ahciport_port_num; 3447 3448 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3449 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3450 3451 /* The port must have been stopped before. */ 3452 ASSERT(!(port_cmd_status & AHCI_CMD_STATUS_ST)); 3453 3454 if (!(port_cmd_status & AHCI_CMD_STATUS_PMA)) { 3455 /* set PMA bit */ 3456 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3457 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3458 port_cmd_status|AHCI_CMD_STATUS_PMA); 3459 3460 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp, 3461 "ahci_alloc_pmult: " 3462 "PxCMD.PMA bit set at port %d.", port); 3463 } 3464 3465 /* Allocate port multiplier information structure */ 3466 if (ahci_portp->ahciport_pmult_info == NULL) { 3467 ahci_portp->ahciport_pmult_info = (ahci_pmult_info_t *) 3468 kmem_zalloc(sizeof (ahci_pmult_info_t), KM_SLEEP); 3469 } 3470 3471 ASSERT(ahci_portp->ahciport_pmult_info != NULL); 3472 } 3473 3474 /* 3475 * ahci_dealloc_pmult() 3476 * 1. Clearing related registers when a port multiplier is detached. 3477 * (Clear PxCMD.PMA while PxCMD.ST is '0') 3478 * 2. Deallocate ahci_pmult_info structure. 3479 * 3480 * NOTE: Must stop port before the function is called. 3481 * WARNING!!! ahciport_mutex should be acquired before the function is 3482 * called. 3483 */ 3484 static void 3485 ahci_dealloc_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3486 { 3487 uint32_t port_cmd_status; 3488 uint8_t port = ahci_portp->ahciport_port_num; 3489 3490 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3491 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3492 3493 if (port_cmd_status & AHCI_CMD_STATUS_PMA) { 3494 /* Clear PMA bit */ 3495 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3496 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3497 (port_cmd_status & (~AHCI_CMD_STATUS_PMA))); 3498 3499 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp, 3500 "ahci_dealloc_pmult: " 3501 "PxCMD.PMA bit cleared at port %d.", port); 3502 } 3503 3504 /* Release port multiplier information structure */ 3505 if (ahci_portp->ahciport_pmult_info != NULL) { 3506 kmem_free(ahci_portp->ahciport_pmult_info, 3507 sizeof (ahci_pmult_info_t)); 3508 ahci_portp->ahciport_pmult_info = NULL; 3509 } 3510 } 3511 3512 /* 3513 * The routine is to initialize a port. First put the port in NOTRunning 3514 * state, then enable port interrupt and clear Serror register. And under 3515 * AHCI_ATTACH case, find device signature and then try to start the port. 3516 * 3517 * Called by 3518 * 1. ahci_initialize_controller 3519 * 2. ahci_intr_phyrdy_change (hotplug) 3520 * 3521 * WARNING!!! ahciport_mutex should be acquired before the function is called. 3522 */ 3523 static int 3524 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3525 ahci_addr_t *addrp) 3526 { 3527 uint32_t port_sstatus, port_task_file, port_cmd_status; 3528 uint8_t port = addrp->aa_port; 3529 boolean_t resuming = B_TRUE; /* processing DDI_RESUME */ 3530 int ret; 3531 3532 ASSERT(mutex_owned(&ahci_portp->ahciport_mutex)); 3533 3534 /* AHCI_ADDR_PORT: We've no idea of the attached device here. */ 3535 ASSERT(AHCI_ADDR_IS_PORT(addrp)); 3536 3537 /* 3538 * At the time being, only probe ports/devices and get the types of 3539 * attached devices during DDI_ATTACH. In fact, the device can be 3540 * changed during power state changes, but at the time being, we 3541 * don't support the situation. 3542 */ 3543 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) { 3544 resuming = B_FALSE; 3545 } else { 3546 /* check for DDI_RESUME case */ 3547 mutex_exit(&ahci_portp->ahciport_mutex); 3548 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3549 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) 3550 resuming = B_FALSE; 3551 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3552 mutex_enter(&ahci_portp->ahciport_mutex); 3553 } 3554 3555 if (resuming) { 3556 /* 3557 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 3558 * and PxFBU registers in case these registers were cleared 3559 * during the suspend. 3560 */ 3561 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3562 "ahci_initialize_port: port %d " 3563 "set PxCLB, PxCLBU, PxFB and PxFBU " 3564 "during resume", port); 3565 3566 /* Config Port Received FIS Base Address */ 3567 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3568 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3569 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3570 3571 /* Config Port Command List Base Address */ 3572 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3573 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 3574 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 3575 } 3576 3577 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3578 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3579 3580 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3581 "ahci_initialize_port: port %d ", port); 3582 3583 /* 3584 * Check whether the port is in NotRunning state, if not, 3585 * put the port in NotRunning state 3586 */ 3587 if (port_cmd_status & 3588 (AHCI_CMD_STATUS_ST | 3589 AHCI_CMD_STATUS_CR | 3590 AHCI_CMD_STATUS_FRE | 3591 AHCI_CMD_STATUS_FR)) { 3592 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 3593 ahci_portp, port); 3594 } 3595 3596 /* Disable interrupt */ 3597 ahci_disable_port_intrs(ahci_ctlp, port); 3598 3599 /* Device is unknown at first */ 3600 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN); 3601 3602 /* Disable the interface power management */ 3603 ahci_disable_interface_pm(ahci_ctlp, port); 3604 3605 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3606 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3607 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3608 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3609 3610 /* Check physcial link status */ 3611 if (SSTATUS_GET_IPM(port_sstatus) == SSTATUS_IPM_NODEV_NOPHYCOM || 3612 SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_NOPHYCOM || 3613 3614 /* Check interface status */ 3615 port_task_file & AHCI_TFD_STS_BSY || 3616 port_task_file & AHCI_TFD_STS_DRQ || 3617 3618 /* Check whether port reset must be executed */ 3619 ahci_ctlp->ahcictl_cap & AHCI_CAP_INIT_PORT_RESET || 3620 3621 /* Always reset port on RESUME */ 3622 resuming != B_FALSE) { 3623 3624 /* Something went wrong, we need do some reset things */ 3625 ret = ahci_port_reset(ahci_ctlp, ahci_portp, addrp); 3626 3627 /* Does port reset succeed on HBA port? */ 3628 if (ret != AHCI_SUCCESS) { 3629 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 3630 "ahci_initialize_port:" 3631 "port reset faild at port %d", port); 3632 return (AHCI_FAILURE); 3633 } 3634 3635 /* Is port failed? */ 3636 if (AHCIPORT_GET_STATE(ahci_portp, addrp) & 3637 SATA_PSTATE_FAILED) { 3638 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 3639 "ahci_initialize_port: port %d state 0x%x", 3640 port, ahci_portp->ahciport_port_state); 3641 return (AHCI_FAILURE); 3642 } 3643 } 3644 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_READY); 3645 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "port %d is ready now.", port); 3646 3647 /* 3648 * Try to get the device signature if the port is not empty. 3649 */ 3650 if (!resuming && ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 3651 ahci_find_dev_signature(ahci_ctlp, ahci_portp, addrp); 3652 3653 /* Return directly if no device connected */ 3654 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3655 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3656 "No device connected to port %d", port); 3657 goto out; 3658 } 3659 3660 /* If this is a port multiplier, we need do some initialization */ 3661 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) { 3662 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 3663 "Port multiplier found at port %d", port); 3664 ahci_alloc_pmult(ahci_ctlp, ahci_portp); 3665 } 3666 3667 /* Try to start the port */ 3668 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 3669 != AHCI_SUCCESS) { 3670 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3671 "failed to start port %d", port); 3672 return (AHCI_FAILURE); 3673 } 3674 out: 3675 /* Enable port interrupts */ 3676 ahci_enable_port_intrs(ahci_ctlp, port); 3677 3678 return (AHCI_SUCCESS); 3679 } 3680 3681 /* 3682 * Handle hardware defect, and check the capabilities. For example, 3683 * power management capabilty and MSI capability. 3684 */ 3685 static int 3686 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 3687 { 3688 ushort_t caps_ptr, cap_count, cap; 3689 #if AHCI_DEBUG 3690 ushort_t pmcap, pmcsr; 3691 ushort_t msimc; 3692 #endif 3693 uint8_t revision; 3694 3695 ahci_ctlp->ahcictl_venid = 3696 pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3697 PCI_CONF_VENID); 3698 3699 ahci_ctlp->ahcictl_devid = 3700 pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3701 PCI_CONF_DEVID); 3702 3703 /* 3704 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 3705 * controllers with 0x00 revision id work on 4-byte aligned buffer, 3706 * which is a bug and was fixed after 0x00 revision id controllers. 3707 * 3708 * Moreover, VT8251 cannot use multiple command slots in the command 3709 * list for non-queued commands because the previous register content 3710 * of PxCI can be re-written in the register write, so a flag will be 3711 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 3712 * 3713 * For VT8251, software reset also has the same defect as the below 3714 * AMD/ATI chipset. That is, software reset will get failed if 0xf 3715 * is filled in pmport field. Therefore, another software reset need 3716 * to be done with 0 filled in pmport field. 3717 */ 3718 if (ahci_ctlp->ahcictl_venid == VIA_VENID) { 3719 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3720 PCI_CONF_REVID); 3721 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3722 "revision id = 0x%x", revision); 3723 if (revision == 0x00) { 3724 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 3725 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3726 "change ddi_attr_align to 0x4", NULL); 3727 } 3728 3729 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NO_MCMDLIST_NONQUEUE; 3730 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3731 "VT8251 cannot use multiple command lists for " 3732 "non-queued commands", NULL); 3733 3734 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT; 3735 } 3736 3737 /* 3738 * AMD/ATI SB600 (0x1002,0x4380) AHCI chipset doesn't support 64-bit 3739 * DMA addressing for communication memory descriptors though S64A bit 3740 * of CAP register declares it supports. Even though 64-bit DMA for 3741 * data buffer works on ASUS M2A-VM with newer BIOS, three other 3742 * motherboards are known not, so both AHCI_CAP_BUF_32BIT_DMA and 3743 * AHCI_CAP_COMMU_32BIT_DMA are set for this controller. 3744 * 3745 * Due to certain hardware issue, the chipset must do port reset during 3746 * initialization, otherwise, when retrieving device signature, 3747 * software reset will get time out. So AHCI_CAP_INIT_PORT_RESET flag 3748 * need to set. 3749 * 3750 * For this chipset software reset will get failure if the pmport of 3751 * Register FIS was set with SATA_PMULT_HOSTPORT (0xf) and no port 3752 * multiplier is connected to the port. In order to fix the issue, 3753 * AHCI_CAP_SRST_NO_HOSTPORT flag need to be set, and once software 3754 * reset got failure, the driver will try to do another software reset 3755 * with pmport 0. 3756 */ 3757 if (ahci_ctlp->ahcictl_venid == 0x1002 && 3758 ahci_ctlp->ahcictl_devid == 0x4380) { 3759 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA; 3760 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA; 3761 ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET; 3762 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT; 3763 3764 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3765 "ATI SB600 cannot do 64-bit DMA for both data buffer and " 3766 "communication memory descriptors though CAP indicates " 3767 "support, so force it to use 32-bit DMA", NULL); 3768 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3769 "ATI SB600 need to do a port reset during initialization", 3770 NULL); 3771 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3772 "ATI SB600 will get software reset failure if pmport " 3773 "is set 0xf and no port multiplier is attached", NULL); 3774 } 3775 3776 /* 3777 * AMD/ATI SB700/710/750/800 and SP5100 AHCI chipset share the same 3778 * vendor ID and device ID (0x1002,0x4391). 3779 * 3780 * SB700/750 AHCI chipset on some boards doesn't support 64-bit 3781 * DMA addressing for communication memory descriptors though S64A bit 3782 * of CAP register declares the support. However, it does support 3783 * 64-bit DMA for data buffer. So only AHCI_CAP_COMMU_32BIT_DMA is 3784 * set for this controller. 3785 * 3786 * SB710 has the same initialization issue as SB600, so it also need 3787 * a port reset. That is AHCI_CAP_INIT_PORT_RESET need to set for it. 3788 * 3789 * SB700 also has the same issue about software reset, and thus 3790 * AHCI_CAP_SRST_NO_HOSTPORT flag also is needed. 3791 */ 3792 if (ahci_ctlp->ahcictl_venid == 0x1002 && 3793 ahci_ctlp->ahcictl_devid == 0x4391) { 3794 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA; 3795 ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET; 3796 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT; 3797 3798 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3799 "ATI SB700/750 cannot do 64-bit DMA for communication " 3800 "memory descriptors though CAP indicates support, " 3801 "so force it to use 32-bit DMA", NULL); 3802 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3803 "ATI SB710 need to do a port reset during initialization", 3804 NULL); 3805 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 3806 "ATI SB700 will get software reset failure if pmport " 3807 "is set 0xf and no port multiplier is attached", NULL); 3808 } 3809 3810 /* 3811 * Check if capabilities list is supported and if so, 3812 * get initial capabilities pointer and clear bits 0,1. 3813 */ 3814 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3815 PCI_CONF_STAT) & PCI_STAT_CAP) { 3816 caps_ptr = P2ALIGN(pci_config_get8( 3817 ahci_ctlp->ahcictl_pci_conf_handle, 3818 PCI_CONF_CAP_PTR), 4); 3819 } else { 3820 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 3821 } 3822 3823 /* 3824 * Walk capabilities if supported. 3825 */ 3826 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 3827 3828 /* 3829 * Check that we haven't exceeded the maximum number of 3830 * capabilities and that the pointer is in a valid range. 3831 */ 3832 if (++cap_count > PCI_CAP_MAX_PTR) { 3833 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 3834 "too many device capabilities", NULL); 3835 return (AHCI_FAILURE); 3836 } 3837 if (caps_ptr < PCI_CAP_PTR_OFF) { 3838 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 3839 "capabilities pointer 0x%x out of range", 3840 caps_ptr); 3841 return (AHCI_FAILURE); 3842 } 3843 3844 /* 3845 * Get next capability and check that it is valid. 3846 * For now, we only support power management. 3847 */ 3848 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3849 caps_ptr); 3850 switch (cap) { 3851 case PCI_CAP_ID_PM: 3852 3853 /* power management supported */ 3854 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 3855 3856 /* Save PMCSR offset */ 3857 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 3858 3859 #if AHCI_DEBUG 3860 pmcap = pci_config_get16( 3861 ahci_ctlp->ahcictl_pci_conf_handle, 3862 caps_ptr + PCI_PMCAP); 3863 pmcsr = pci_config_get16( 3864 ahci_ctlp->ahcictl_pci_conf_handle, 3865 ahci_ctlp->ahcictl_pmcsr_offset); 3866 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3867 "Power Management capability found PCI_PMCAP " 3868 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 3869 if ((pmcap & 0x3) == 0x3) 3870 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3871 "PCI Power Management Interface " 3872 "spec 1.2 compliant", NULL); 3873 #endif 3874 break; 3875 3876 case PCI_CAP_ID_MSI: 3877 #if AHCI_DEBUG 3878 msimc = pci_config_get16( 3879 ahci_ctlp->ahcictl_pci_conf_handle, 3880 caps_ptr + PCI_MSI_CTRL); 3881 AHCIDBG(AHCIDBG_MSI, ahci_ctlp, 3882 "Message Signaled Interrupt capability found " 3883 "MSICAP_MC.MMC = 0x%x", (msimc & 0xe) >> 1); 3884 #endif 3885 AHCIDBG(AHCIDBG_MSI, ahci_ctlp, 3886 "MSI capability found", NULL); 3887 break; 3888 3889 case PCI_CAP_ID_PCIX: 3890 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3891 "PCI-X capability found", NULL); 3892 break; 3893 3894 case PCI_CAP_ID_PCI_E: 3895 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3896 "PCI Express capability found", NULL); 3897 break; 3898 3899 case PCI_CAP_ID_MSI_X: 3900 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3901 "MSI-X capability found", NULL); 3902 break; 3903 3904 case PCI_CAP_ID_SATA: 3905 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3906 "SATA capability found", NULL); 3907 break; 3908 3909 case PCI_CAP_ID_VS: 3910 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3911 "Vendor Specific capability found", NULL); 3912 break; 3913 3914 default: 3915 AHCIDBG(AHCIDBG_PM, ahci_ctlp, 3916 "unrecognized capability 0x%x", cap); 3917 break; 3918 } 3919 3920 /* 3921 * Get next capabilities pointer and clear bits 0,1. 3922 */ 3923 caps_ptr = P2ALIGN(pci_config_get8( 3924 ahci_ctlp->ahcictl_pci_conf_handle, 3925 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3926 } 3927 3928 return (AHCI_SUCCESS); 3929 } 3930 3931 /* 3932 * Read/Write a register at port multiplier by SATA READ PORTMULT / SATA WRITE 3933 * PORTMULT command. SYNC & POLLING mode is used. 3934 * 3935 * WARNING!!! ahciport_mutex should be acquired before the function 3936 * is called. 3937 */ 3938 static int 3939 ahci_rdwr_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp, 3940 uint8_t regn, uint32_t *pregv, uint8_t type) 3941 { 3942 ahci_port_t *ahci_portp; 3943 ahci_addr_t pmult_addr; 3944 sata_pkt_t *spkt; 3945 sata_cmd_t *scmd; 3946 sata_device_t sata_device; 3947 uint8_t port = addrp->aa_port; 3948 uint8_t pmport = addrp->aa_pmport; 3949 uint8_t cport; 3950 uint32_t intr_mask; 3951 int rval; 3952 char portstr[10]; 3953 3954 SET_PORTSTR(portstr, addrp); 3955 cport = ahci_ctlp->ahcictl_port_to_cport[port]; 3956 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3957 3958 ASSERT(AHCI_ADDR_IS_PMPORT(addrp) || AHCI_ADDR_IS_PMULT(addrp)); 3959 ASSERT(mutex_owned(&ahci_portp->ahciport_mutex)); 3960 3961 /* Check the existence of the port multiplier */ 3962 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) 3963 return (AHCI_FAILURE); 3964 3965 /* Request a READ/WRITE PORTMULT sata packet. */ 3966 bzero(&sata_device, sizeof (sata_device_t)); 3967 sata_device.satadev_addr.cport = cport; 3968 sata_device.satadev_addr.pmport = pmport; 3969 sata_device.satadev_addr.qual = SATA_ADDR_PMULT; 3970 sata_device.satadev_rev = SATA_DEVICE_REV; 3971 3972 /* 3973 * Make sure no command is outstanding here. All R/W PMULT requests 3974 * come from 3975 * 3976 * 1. ahci_attach() 3977 * The port should be empty. 3978 * 3979 * 2. ahci_tran_probe_port() 3980 * Any request from SATA framework (via ahci_tran_start) should be 3981 * rejected if R/W PMULT command is outstanding. 3982 * 3983 * If we are doing mopping, do not check those flags because no 3984 * command will be actually outstanding. 3985 * 3986 * If the port has been occupied by any other commands, the probe 3987 * function will return a SATA_RETRY. SATA framework will retry 3988 * later. 3989 */ 3990 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) { 3991 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 3992 "R/W PMULT failed: R/W PMULT in progress at port %d.", 3993 port, ahci_portp->ahciport_flags); 3994 return (AHCI_FAILURE); 3995 } 3996 3997 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && ( 3998 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) || 3999 NCQ_CMD_IN_PROGRESS(ahci_portp) || 4000 NON_NCQ_CMD_IN_PROGRESS(ahci_portp))) { 4001 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 4002 "R/W PMULT failed: port %d is occupied (flags 0x%x).", 4003 port, ahci_portp->ahciport_flags); 4004 return (AHCI_FAILURE); 4005 } 4006 4007 /* 4008 * The port multiplier is gone. This may happen when 4009 * 1. Cutting off the power of an enclosure. The device lose the power 4010 * before port multiplier. 4011 * 2. Disconnecting the port multiplier during hot-plugging a sub-drive. 4012 * 4013 * The issued command should be aborted and the following command 4014 * should not be continued. 4015 */ 4016 if (!(ahci_portp->ahciport_port_state & SATA_STATE_READY)) { 4017 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 4018 "READ/WRITE PMULT failed: " 4019 "port-mult is removed from port %d", port); 4020 return (AHCI_FAILURE); 4021 } 4022 4023 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDWR_PMULT; 4024 4025 spkt = sata_get_rdwr_pmult_pkt(ahci_ctlp->ahcictl_dip, 4026 &sata_device, regn, *pregv, type); 4027 4028 /* 4029 * READ/WRITE PORTMULT command is intended to sent to the control port 4030 * of the port multiplier. 4031 */ 4032 AHCI_ADDR_SET_PMULT(&pmult_addr, addrp->aa_port); 4033 4034 ahci_portp->ahciport_rdwr_pmult_pkt = spkt; 4035 4036 /* No interrupt here. Store the interrupt enable mask. */ 4037 intr_mask = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4038 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4039 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4040 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 4041 4042 rval = ahci_do_sync_start(ahci_ctlp, ahci_portp, &pmult_addr, spkt); 4043 4044 if (rval == AHCI_SUCCESS && 4045 spkt->satapkt_reason == SATA_PKT_COMPLETED) { 4046 if (type == SATA_RDWR_PMULT_PKT_TYPE_READ) { 4047 scmd = &spkt->satapkt_cmd; 4048 *pregv = scmd->satacmd_lba_high_lsb << 24 | 4049 scmd->satacmd_lba_mid_lsb << 16 | 4050 scmd->satacmd_lba_low_lsb << 8 | 4051 scmd->satacmd_sec_count_lsb; 4052 } 4053 } else { 4054 /* Failed or not completed. */ 4055 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 4056 "ahci_rdwr_pmult: cannot [%s] %s[%d] at port %s", 4057 type == SATA_RDWR_PMULT_PKT_TYPE_READ?"Read":"Write", 4058 AHCI_ADDR_IS_PMULT(addrp)?"gscr":"pscr", regn, portstr); 4059 rval = AHCI_FAILURE; 4060 } 4061 out: 4062 /* Restore the interrupt mask */ 4063 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4064 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), intr_mask); 4065 4066 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RDWR_PMULT; 4067 ahci_portp->ahciport_rdwr_pmult_pkt = NULL; 4068 sata_free_rdwr_pmult_pkt(spkt); 4069 return (rval); 4070 } 4071 4072 static int 4073 ahci_read_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp, 4074 uint8_t regn, uint32_t *pregv) 4075 { 4076 return ahci_rdwr_pmult(ahci_ctlp, addrp, regn, pregv, 4077 SATA_RDWR_PMULT_PKT_TYPE_READ); 4078 } 4079 4080 static int 4081 ahci_write_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp, 4082 uint8_t regn, uint32_t regv) 4083 { 4084 return ahci_rdwr_pmult(ahci_ctlp, addrp, regn, ®v, 4085 SATA_RDWR_PMULT_PKT_TYPE_WRITE); 4086 } 4087 4088 #define READ_PMULT(addrp, r, pv, out) \ 4089 if (ahci_read_pmult(ahci_ctlp, addrp, r, pv) != AHCI_SUCCESS) \ 4090 goto out; 4091 4092 #define WRITE_PMULT(addrp, r, v, out) \ 4093 if (ahci_write_pmult(ahci_ctlp, addrp, r, v) != AHCI_SUCCESS) \ 4094 goto out; 4095 4096 /* 4097 * Update sata registers on port multiplier, including GSCR/PSCR registers. 4098 * ahci_update_pmult_gscr() 4099 * ahci_update_pmult_pscr() 4100 * 4101 * WARNING!!! ahciport_mutex should be acquired before those functions 4102 * get called. 4103 */ 4104 static int 4105 ahci_update_pmult_gscr(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp, 4106 sata_pmult_gscr_t *sg) 4107 { 4108 READ_PMULT(addrp, SATA_PMULT_GSCR0, &sg->gscr0, err); 4109 READ_PMULT(addrp, SATA_PMULT_GSCR1, &sg->gscr1, err); 4110 READ_PMULT(addrp, SATA_PMULT_GSCR2, &sg->gscr2, err); 4111 READ_PMULT(addrp, SATA_PMULT_GSCR64, &sg->gscr64, err); 4112 4113 return (AHCI_SUCCESS); 4114 4115 err: /* R/W PMULT error */ 4116 return (AHCI_FAILURE); 4117 } 4118 4119 static int 4120 ahci_update_pmult_pscr(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp, 4121 sata_device_t *sd) 4122 { 4123 ASSERT(AHCI_ADDR_IS_PMPORT(addrp)); 4124 4125 READ_PMULT(addrp, SATA_PMULT_REG_SSTS, &sd->satadev_scr.sstatus, err); 4126 READ_PMULT(addrp, SATA_PMULT_REG_SERR, &sd->satadev_scr.serror, err); 4127 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &sd->satadev_scr.scontrol, err); 4128 READ_PMULT(addrp, SATA_PMULT_REG_SACT, &sd->satadev_scr.sactive, err); 4129 4130 return (AHCI_SUCCESS); 4131 4132 err: /* R/W PMULT error */ 4133 return (AHCI_FAILURE); 4134 } 4135 4136 /* 4137 * ahci_initialize_pmult() 4138 * 4139 * Initialize a port multiplier, including 4140 * 1. Enable FEATURES register at port multiplier. (SATA Chp.16) 4141 * 2. Redefine MASK register. (SATA Chap 16.?) 4142 * 4143 * WARNING!!! ahciport_mutex should be acquired before the function 4144 * is called. 4145 */ 4146 static int 4147 ahci_initialize_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4148 ahci_addr_t *addrp, sata_device_t *sd) 4149 { 4150 sata_pmult_gscr_t sg; 4151 uint32_t gscr64; 4152 uint8_t port = addrp->aa_port; 4153 4154 ASSERT(mutex_owned(&ahci_portp->ahciport_mutex)); 4155 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 4156 "[Initialize] Port-multiplier at port %d.", port); 4157 4158 /* 4159 * Enable features of port multiplier. Currently only 4160 * Asynchronous Notification is enabled. 4161 */ 4162 /* Check gscr64 for supported features. */ 4163 READ_PMULT(addrp, SATA_PMULT_GSCR64, &gscr64, err); 4164 4165 if (gscr64 & SATA_PMULT_CAP_SNOTIF) { 4166 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 4167 "port %d: Port Multiplier supports " 4168 "Asynchronous Notification.", port); 4169 4170 /* Write to gscr96 to enabled features */ 4171 WRITE_PMULT(addrp, SATA_PMULT_GSCR96, 4172 SATA_PMULT_CAP_SNOTIF, err); 4173 4174 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4175 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port), 4176 AHCI_SNOTIF_CLEAR_ALL); 4177 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 4178 "port %d: PMult PxSNTF cleared.", port); 4179 4180 } 4181 4182 /* 4183 * Now we need to update gscr33 register to enable hot-plug interrupt 4184 * for sub devices behind port multiplier. 4185 */ 4186 WRITE_PMULT(addrp, SATA_PMULT_GSCR33, (0x1ffff), err); 4187 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 4188 "port %d: gscr33 mask set to %x.", port, (0x1ffff)); 4189 4190 /* 4191 * Fetch the number of device ports of the port multiplier 4192 */ 4193 if (ahci_update_pmult_gscr(ahci_ctlp, addrp, &sg) != AHCI_SUCCESS) 4194 return (AHCI_FAILURE); 4195 4196 /* Register the port multiplier to SATA Framework. */ 4197 mutex_exit(&ahci_portp->ahciport_mutex); 4198 sata_register_pmult(ahci_ctlp->ahcictl_dip, sd, &sg); 4199 mutex_enter(&ahci_portp->ahciport_mutex); 4200 4201 ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports = 4202 sd->satadev_add_info & SATA_PMULT_PORTNUM_MASK; 4203 4204 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 4205 "port %d: pmult sub-port number updated to %x.", port, 4206 ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports); 4207 4208 /* Till now port-mult is successfully initialized */ 4209 ahci_portp->ahciport_port_state |= SATA_DSTATE_PMULT_INIT; 4210 return (AHCI_SUCCESS); 4211 4212 err: /* R/W PMULT error */ 4213 return (AHCI_FAILURE); 4214 } 4215 4216 /* 4217 * Initialize a port multiplier port. According to spec, firstly we need 4218 * issue a COMRESET, then a software reset to get its signature. 4219 * 4220 * NOTE: This function should only be called in ahci_probe_pmport() 4221 * WARNING!!! ahciport_mutex should be acquired before the function. 4222 */ 4223 static int 4224 ahci_initialize_pmport(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4225 ahci_addr_t *addrp) 4226 { 4227 uint32_t finished_tags = 0, reset_tags = 0, slot_status = 0; 4228 uint8_t port = addrp->aa_port; 4229 uint8_t pmport = addrp->aa_pmport; 4230 int ret = AHCI_FAILURE; 4231 4232 ASSERT(AHCI_ADDR_IS_PMPORT(addrp)); 4233 4234 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4235 "ahci_initialize_pmport: port %d:%d", port, pmport); 4236 4237 /* Check HBA port state */ 4238 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 4239 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 4240 "ahci_initialize_pmport:" 4241 "port %d:%d Port Multiplier is failed.", 4242 port, pmport); 4243 return (AHCI_FAILURE); 4244 } 4245 4246 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) { 4247 return (AHCI_FAILURE); 4248 } 4249 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_HOTPLUG; 4250 4251 /* Checking for outstanding commands */ 4252 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4253 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4254 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4255 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 4256 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4257 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4258 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4259 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 4260 } 4261 4262 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 4263 ahci_portp->ahciport_mop_in_progress++; 4264 4265 /* Clear status */ 4266 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_UNKNOWN); 4267 4268 /* Firstly assume an unknown device */ 4269 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN); 4270 4271 ahci_disable_port_intrs(ahci_ctlp, port); 4272 4273 /* port reset is necessary for port multiplier port */ 4274 if (ahci_pmport_reset(ahci_ctlp, ahci_portp, addrp) != AHCI_SUCCESS) { 4275 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 4276 "ahci_initialize_pmport:" 4277 "port reset failed at port %d:%d", 4278 port, pmport); 4279 goto out; 4280 } 4281 4282 /* Is port failed? */ 4283 if (AHCIPORT_GET_STATE(ahci_portp, addrp) & 4284 SATA_PSTATE_FAILED) { 4285 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4286 "ahci_initialize_pmport: port %d:%d failed. " 4287 "state = 0x%x", port, pmport, 4288 ahci_portp->ahciport_port_state); 4289 goto out; 4290 } 4291 4292 /* Is there any device attached? */ 4293 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, addrp) 4294 == SATA_DTYPE_NONE) { 4295 /* Do not waste time on an empty port */ 4296 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 4297 "ahci_initialize_pmport: No device is found " 4298 "at port %d:%d", port, pmport); 4299 ret = AHCI_SUCCESS; 4300 goto out; 4301 } 4302 4303 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_READY); 4304 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 4305 "port %d:%d is ready now.", port, pmport); 4306 4307 /* 4308 * Till now we can assure a device attached to that HBA port and work 4309 * correctly. Now try to get the device signature. This is an optional 4310 * step. If failed, unknown device is assumed, then SATA module will 4311 * continue to use IDENTIFY DEVICE to get the information of the 4312 * device. 4313 */ 4314 ahci_find_dev_signature(ahci_ctlp, ahci_portp, addrp); 4315 4316 ret = AHCI_SUCCESS; 4317 4318 out: 4319 /* Next try to mop the pending commands */ 4320 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 4321 finished_tags = ahci_portp->ahciport_pending_tags & 4322 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 4323 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 4324 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4325 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 4326 reset_tags &= ~finished_tags; 4327 4328 ahci_mop_commands(ahci_ctlp, 4329 ahci_portp, 4330 slot_status, 4331 0, /* failed tags */ 4332 0, /* timeout tags */ 4333 0, /* aborted tags */ 4334 reset_tags); /* reset tags */ 4335 4336 /* Clear PxSNTF register if supported. */ 4337 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SNTF) { 4338 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4339 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port), 4340 AHCI_SNOTIF_CLEAR_ALL); 4341 } 4342 4343 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_HOTPLUG; 4344 ahci_enable_port_intrs(ahci_ctlp, port); 4345 return (ret); 4346 } 4347 4348 /* 4349 * ahci_probe_pmult() 4350 * 4351 * This function will be called to probe a port multiplier, which will 4352 * handle hotplug events on port multiplier ports. 4353 * 4354 * NOTE: Only called from ahci_tran_probe_port() 4355 * WARNING!!! ahciport_mutex should be acquired before the function is called. 4356 */ 4357 static int 4358 ahci_probe_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4359 ahci_addr_t *addrp) 4360 { 4361 sata_device_t sdevice; 4362 ahci_addr_t pmport_addr; 4363 uint32_t gscr32, port_hotplug_tags; 4364 uint32_t pmport_sstatus; 4365 int dev_exists_now = 0, dev_existed_previously = 0; 4366 uint8_t port = addrp->aa_port; 4367 int npmport; 4368 4369 /* The bits in GSCR32 refers to the pmport that has a hot-plug event. */ 4370 READ_PMULT(addrp, SATA_PMULT_GSCR32, &gscr32, err); 4371 port_hotplug_tags = gscr32 & AHCI_PMPORT_MASK(ahci_portp); 4372 4373 do { 4374 npmport = ddi_ffs(port_hotplug_tags) - 1; 4375 if (npmport == -1) 4376 /* no pending hot plug events. */ 4377 return (AHCI_SUCCESS); 4378 4379 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp, 4380 "hot-plug event at port %d:%d", port, npmport); 4381 4382 AHCI_ADDR_SET_PMPORT(&pmport_addr, port, (uint8_t)npmport); 4383 4384 /* Check previous device at that port */ 4385 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &pmport_addr) 4386 != SATA_DTYPE_NONE) 4387 dev_existed_previously = 1; 4388 4389 /* PxSStatus tells the presence of device. */ 4390 READ_PMULT(&pmport_addr, SATA_PMULT_REG_SSTS, 4391 &pmport_sstatus, err); 4392 4393 if (SSTATUS_GET_DET(pmport_sstatus) == 4394 SSTATUS_DET_DEVPRE_PHYCOM) 4395 dev_exists_now = 1; 4396 4397 /* 4398 * Clear PxSERR is critical. The transition from 0 to 1 will 4399 * emit a FIS which generates an asynchronous notification 4400 * event at controller. If we fail to clear the PxSERR, the 4401 * Async Notif events will no longer be activated on this 4402 * pmport. 4403 */ 4404 WRITE_PMULT(&pmport_addr, SATA_PMULT_REG_SERR, 4405 AHCI_SERROR_CLEAR_ALL, err); 4406 4407 bzero((void *)&sdevice, sizeof (sata_device_t)); 4408 sdevice.satadev_addr.cport = ahci_ctlp-> 4409 ahcictl_port_to_cport[port]; 4410 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT; 4411 sdevice.satadev_addr.pmport = (uint8_t)npmport; 4412 sdevice.satadev_state = SATA_PSTATE_PWRON; 4413 4414 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp, 4415 "[Existence] %d -> %d", dev_existed_previously, 4416 dev_exists_now); 4417 4418 if (dev_exists_now) { 4419 if (dev_existed_previously) { 4420 /* Link (may) not change: Exist -> Exist * */ 4421 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp, 4422 "ahci_probe_pmult: port %d:%d " 4423 "device link lost/established", 4424 port, npmport); 4425 4426 mutex_exit(&ahci_portp->ahciport_mutex); 4427 sata_hba_event_notify( 4428 ahci_ctlp->ahcictl_sata_hba_tran-> 4429 sata_tran_hba_dip, 4430 &sdevice, 4431 SATA_EVNT_LINK_LOST| 4432 SATA_EVNT_LINK_ESTABLISHED); 4433 mutex_enter(&ahci_portp->ahciport_mutex); 4434 } else { 4435 /* Link change: None -> Exist */ 4436 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp, 4437 "ahci_probe_pmult: port %d:%d " 4438 "device link established", port, npmport); 4439 4440 /* Clear port state */ 4441 AHCIPORT_SET_STATE(ahci_portp, &pmport_addr, 4442 SATA_STATE_UNKNOWN); 4443 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp, 4444 "ahci_probe_pmult: port %d " 4445 "ahciport_port_state [Cleared].", port); 4446 4447 mutex_exit(&ahci_portp->ahciport_mutex); 4448 sata_hba_event_notify( 4449 ahci_ctlp->ahcictl_sata_hba_tran-> 4450 sata_tran_hba_dip, 4451 &sdevice, 4452 SATA_EVNT_LINK_ESTABLISHED); 4453 mutex_enter(&ahci_portp->ahciport_mutex); 4454 } 4455 } else { /* No device exists now */ 4456 if (dev_existed_previously) { 4457 4458 /* Link change: Exist -> None */ 4459 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp, 4460 "ahci_probe_pmult: port %d:%d " 4461 "device link lost", port, npmport); 4462 4463 /* An existing device is lost. */ 4464 AHCIPORT_SET_STATE(ahci_portp, &pmport_addr, 4465 SATA_STATE_UNKNOWN); 4466 AHCIPORT_SET_DEV_TYPE(ahci_portp, &pmport_addr, 4467 SATA_DTYPE_NONE); 4468 4469 mutex_exit(&ahci_portp->ahciport_mutex); 4470 sata_hba_event_notify( 4471 ahci_ctlp->ahcictl_sata_hba_tran-> 4472 sata_tran_hba_dip, 4473 &sdevice, 4474 SATA_EVNT_LINK_LOST); 4475 mutex_enter(&ahci_portp->ahciport_mutex); 4476 } 4477 } 4478 4479 CLEAR_BIT(port_hotplug_tags, npmport); 4480 } while (port_hotplug_tags != 0); 4481 4482 return (AHCI_SUCCESS); 4483 4484 err: /* R/W PMULT error */ 4485 return (AHCI_FAILURE); 4486 } 4487 4488 /* 4489 * Probe and initialize a port multiplier port. 4490 * A port multiplier port could only be initilaizer here. 4491 * 4492 * WARNING!!! ahcictl_mutex should be acquired before the function 4493 * is called. 4494 */ 4495 static int 4496 ahci_probe_pmport(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4497 ahci_addr_t *addrp, sata_device_t *sd) 4498 { 4499 uint32_t port_state; 4500 uint8_t port = addrp->aa_port; 4501 ahci_addr_t addr_pmult; 4502 4503 /* 4504 * Check the parent - port multiplier first. 4505 */ 4506 4507 /* 4508 * Parent port multiplier might have been removed. This event will be 4509 * ignored and failure. 4510 */ 4511 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 4512 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) { 4513 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 4514 "ahci_tran_probe_port: " 4515 "parent device removed, ignore event.", NULL); 4516 4517 return (AHCI_FAILURE); 4518 } 4519 4520 /* The port is ready? */ 4521 port_state = ahci_portp->ahciport_port_state; 4522 if (!(port_state & SATA_STATE_READY)) { 4523 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 4524 "ahci_tran_probe_port: " 4525 "parent port-mult is NOT ready.", NULL); 4526 4527 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 4528 ahci_portp, port, AHCI_PORT_RESET, NULL) != 4529 AHCI_SUCCESS) { 4530 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp, 4531 "ahci_tran_probe_port: " 4532 "restart port-mult failed.", NULL); 4533 return (AHCI_FAILURE); 4534 } 4535 } 4536 4537 /* 4538 * If port-mult is restarted due to some reason, we need 4539 * re-initialized the PMult. 4540 */ 4541 if (!(port_state & SATA_DSTATE_PMULT_INIT)) { 4542 /* Initialize registers on a port multiplier */ 4543 AHCI_ADDR_SET_PMULT(&addr_pmult, addrp->aa_port); 4544 if (ahci_initialize_pmult(ahci_ctlp, ahci_portp, 4545 &addr_pmult, sd) != AHCI_SUCCESS) 4546 return (AHCI_FAILURE); 4547 } 4548 4549 /* 4550 * Then we check the port-mult port 4551 */ 4552 /* Is this pmport initialized? */ 4553 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp); 4554 if (!(port_state & SATA_STATE_READY)) { 4555 4556 /* ahci_initialize_pmport() will set READY state */ 4557 if (ahci_initialize_pmport(ahci_ctlp, 4558 ahci_portp, addrp) != AHCI_SUCCESS) 4559 return (AHCI_FAILURE); 4560 } 4561 4562 return (AHCI_SUCCESS); 4563 } 4564 4565 /* 4566 * AHCI device reset ...; a single device on one of the ports is reset, 4567 * but the HBA and physical communication remain intact. This is the 4568 * least intrusive. 4569 * 4570 * When issuing a software reset sequence, there should not be other 4571 * commands in the command list, so we will first clear and then re-set 4572 * PxCMD.ST to clear PxCI. And before issuing the software reset, 4573 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 4574 * cleared unless command list override (PxCMD.CLO) is supported. 4575 * 4576 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 4577 * set before the function is called. 4578 */ 4579 static int 4580 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4581 ahci_addr_t *addrp) 4582 { 4583 ahci_fis_h2d_register_t *h2d_register_fisp; 4584 ahci_cmd_table_t *cmd_table; 4585 ahci_cmd_header_t *cmd_header; 4586 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 4587 int slot, loop_count; 4588 uint8_t port = addrp->aa_port; 4589 uint8_t pmport = addrp->aa_pmport; 4590 int rval = AHCI_FAILURE; 4591 4592 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 4593 "port %d:%d device software resetting (FIS)", port, pmport); 4594 4595 /* First clear PxCMD.ST (AHCI v1.2 10.4.1) */ 4596 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 4597 port) != AHCI_SUCCESS) { 4598 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4599 "ahci_software_reset: cannot stop HBA port %d.", port); 4600 goto out; 4601 } 4602 4603 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 4604 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4605 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 4606 4607 if (port_task_file & AHCI_TFD_STS_BSY || 4608 port_task_file & AHCI_TFD_STS_DRQ) { 4609 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_SCLO)) { 4610 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4611 "PxTFD.STS.BSY/DRQ is set (PxTFD=0x%x), " 4612 "cannot issue a software reset.", port_task_file); 4613 goto out; 4614 } 4615 4616 /* 4617 * If HBA Support CLO, as Command List Override (CAP.SCLO is 4618 * set), PxCMD.CLO bit should be set before set PxCMD.ST, in 4619 * order to clear PxTFD.STS.BSY and PxTFD.STS.DRQ. 4620 */ 4621 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4622 "PxTFD.STS.BSY/DRQ is set, try SCLO.", NULL) 4623 4624 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4625 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4626 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4627 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4628 port_cmd_status|AHCI_CMD_STATUS_CLO); 4629 4630 /* Waiting till PxCMD.SCLO bit is cleared */ 4631 loop_count = 0; 4632 do { 4633 /* Wait for 10 millisec */ 4634 drv_usecwait(AHCI_10MS_USECS); 4635 4636 /* We are effectively timing out after 1 sec. */ 4637 if (loop_count++ > 100) { 4638 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4639 "SCLO time out. port %d is busy.", port); 4640 goto out; 4641 } 4642 4643 port_cmd_status = 4644 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4645 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4646 } while (port_cmd_status & AHCI_CMD_STATUS_CLO); 4647 4648 /* Re-check */ 4649 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4650 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 4651 if (port_task_file & AHCI_TFD_STS_BSY || 4652 port_task_file & AHCI_TFD_STS_DRQ) { 4653 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4654 "SCLO cannot clear PxTFD.STS.BSY/DRQ (PxTFD=0x%x)", 4655 port_task_file); 4656 goto out; 4657 } 4658 } 4659 4660 /* Then start port */ 4661 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4662 != AHCI_SUCCESS) { 4663 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4664 "ahci_software_reset: cannot start AHCI port %d.", port); 4665 goto out; 4666 } 4667 4668 /* 4669 * When ahci_port.ahciport_mop_in_progress is set, A non-zero 4670 * ahci_port.ahciport_pending_ncq_tags may fail 4671 * ahci_claim_free_slot(). Actually according to spec, by clearing 4672 * PxCMD.ST there is no command outstanding while executing software 4673 * reseting. Hence we directly use slot 0 instead of 4674 * ahci_claim_free_slot(). 4675 */ 4676 slot = 0; 4677 4678 /* Now send the first H2D Register FIS with SRST set to 1 */ 4679 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 4680 bzero((void *)cmd_table, ahci_cmd_table_size); 4681 4682 h2d_register_fisp = 4683 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 4684 4685 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 4686 SET_FIS_PMP(h2d_register_fisp, pmport); 4687 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 4688 4689 /* Set Command Header in Command List */ 4690 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 4691 BZERO_DESCR_INFO(cmd_header); 4692 BZERO_PRD_BYTE_COUNT(cmd_header); 4693 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 4694 SET_PORT_MULTI_PORT(cmd_header, pmport); 4695 4696 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 4697 SET_RESET(cmd_header, 1); 4698 SET_WRITE(cmd_header, 1); 4699 4700 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4701 0, 4702 ahci_cmd_table_size, 4703 DDI_DMA_SYNC_FORDEV); 4704 4705 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 4706 slot * sizeof (ahci_cmd_header_t), 4707 sizeof (ahci_cmd_header_t), 4708 DDI_DMA_SYNC_FORDEV); 4709 4710 /* Indicate to the HBA that a command is active. */ 4711 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4712 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 4713 (0x1 << slot)); 4714 4715 loop_count = 0; 4716 4717 /* Loop till the first command is finished */ 4718 do { 4719 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4720 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4721 4722 /* We are effectively timing out after 1 sec. */ 4723 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 4724 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4725 "the first SRST FIS is timed out, " 4726 "loop_count = %d", loop_count); 4727 goto out; 4728 } 4729 /* Wait for 10 millisec */ 4730 drv_usecwait(AHCI_10MS_USECS); 4731 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 4732 4733 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp, 4734 "ahci_software_reset: 1st loop count: %d, " 4735 "port_cmd_issue = 0x%x, slot = 0x%x", 4736 loop_count, port_cmd_issue, slot); 4737 4738 /* According to ATA spec, we need wait at least 5 microsecs here. */ 4739 drv_usecwait(AHCI_1MS_USECS); 4740 4741 /* Now send the second H2D Register FIS with SRST cleard to zero */ 4742 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 4743 bzero((void *)cmd_table, ahci_cmd_table_size); 4744 4745 h2d_register_fisp = 4746 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 4747 4748 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 4749 SET_FIS_PMP(h2d_register_fisp, pmport); 4750 4751 /* Set Command Header in Command List */ 4752 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 4753 BZERO_DESCR_INFO(cmd_header); 4754 BZERO_PRD_BYTE_COUNT(cmd_header); 4755 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 4756 SET_PORT_MULTI_PORT(cmd_header, pmport); 4757 4758 SET_WRITE(cmd_header, 1); 4759 4760 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4761 0, 4762 ahci_cmd_table_size, 4763 DDI_DMA_SYNC_FORDEV); 4764 4765 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 4766 slot * sizeof (ahci_cmd_header_t), 4767 sizeof (ahci_cmd_header_t), 4768 DDI_DMA_SYNC_FORDEV); 4769 4770 /* Indicate to the HBA that a command is active. */ 4771 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4772 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 4773 (0x1 << slot)); 4774 4775 loop_count = 0; 4776 4777 /* Loop till the second command is finished */ 4778 do { 4779 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4780 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4781 4782 /* We are effectively timing out after 1 sec. */ 4783 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 4784 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4785 "the second SRST FIS is timed out, " 4786 "loop_count = %d", loop_count); 4787 goto out; 4788 } 4789 4790 /* Wait for 10 millisec */ 4791 drv_usecwait(AHCI_10MS_USECS); 4792 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 4793 4794 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp, 4795 "ahci_software_reset: 2nd loop count: %d, " 4796 "port_cmd_issue = 0x%x, slot = 0x%x", 4797 loop_count, port_cmd_issue, slot); 4798 4799 rval = AHCI_SUCCESS; 4800 out: 4801 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4802 "ahci_software_reset: %s at port %d:%d", 4803 rval == AHCI_SUCCESS ? "succeed" : "failed", 4804 port, pmport); 4805 4806 return (rval); 4807 } 4808 4809 /* 4810 * AHCI port reset ...; the physical communication between the HBA and device 4811 * on a port are disabled. This is more intrusive. 4812 * 4813 * When an HBA or port reset occurs, Phy communication is going to 4814 * be re-established with the device through a COMRESET followed by the 4815 * normal out-of-band communication sequence defined in Serial ATA. AT 4816 * the end of reset, the device, if working properly, will send a D2H 4817 * Register FIS, which contains the device signature. When the HBA receives 4818 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 4819 * the PxSIG register with the signature. 4820 * 4821 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 4822 * to individually spin-up attached devices. Please refer to chapter 10.9 of 4823 * AHCI 1.0 spec. 4824 */ 4825 /* 4826 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 4827 * cleared before the function is called. 4828 */ 4829 static int 4830 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4831 ahci_addr_t *addrp) 4832 { 4833 ahci_addr_t pmult_addr; 4834 uint32_t cap_status, port_cmd_status; 4835 uint32_t port_scontrol, port_sstatus, port_serror; 4836 uint32_t port_intr_status, port_task_file; 4837 uint32_t port_state; 4838 uint8_t port = addrp->aa_port; 4839 4840 int loop_count; 4841 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 4842 4843 /* Target is a port multiplier port? */ 4844 if (AHCI_ADDR_IS_PMPORT(addrp)) 4845 return (ahci_pmport_reset(ahci_ctlp, ahci_portp, addrp)); 4846 4847 /* Otherwise it must be an HBA port. */ 4848 ASSERT(AHCI_ADDR_IS_PORT(addrp)); 4849 4850 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4851 "Port %d port resetting...", port); 4852 ahci_portp->ahciport_port_state = 0; 4853 4854 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4855 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4856 4857 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4858 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4859 4860 if (cap_status & AHCI_HBA_CAP_SSS) { 4861 /* 4862 * HBA support staggered spin-up, if the port has 4863 * not spin up yet, then force it to do spin-up 4864 */ 4865 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 4866 if (!(ahci_portp->ahciport_flags 4867 & AHCI_PORT_FLAG_SPINUP)) { 4868 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 4869 "Port %d PxCMD.SUD is zero, force " 4870 "it to do spin-up", port); 4871 ahci_portp->ahciport_flags |= 4872 AHCI_PORT_FLAG_SPINUP; 4873 } 4874 } 4875 } else { 4876 /* 4877 * HBA doesn't support stagger spin-up, force it 4878 * to do normal COMRESET 4879 */ 4880 if (ahci_portp->ahciport_flags & 4881 AHCI_PORT_FLAG_SPINUP) { 4882 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 4883 "HBA does not support staggered spin-up " 4884 "force it to do normal COMRESET", NULL); 4885 ahci_portp->ahciport_flags &= 4886 ~AHCI_PORT_FLAG_SPINUP; 4887 } 4888 } 4889 4890 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 4891 /* Do normal COMRESET */ 4892 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 4893 "ahci_port_reset: do normal COMRESET", port); 4894 4895 /* 4896 * According to the spec, SUD bit should be set here, 4897 * but JMicron JMB363 doesn't follow it, so remove 4898 * the assertion, and just print a debug message. 4899 */ 4900 #if AHCI_DEBUG 4901 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 4902 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 4903 "port %d SUD bit not set", port) 4904 #endif 4905 4906 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4907 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 4908 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 4909 4910 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4911 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 4912 port_scontrol); 4913 4914 /* Enable PxCMD.FRE to read device */ 4915 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4916 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4917 port_cmd_status|AHCI_CMD_STATUS_FRE); 4918 4919 /* 4920 * Give time for COMRESET to percolate, according to the AHCI 4921 * spec, software shall wait at least 1 millisecond before 4922 * clearing PxSCTL.DET 4923 */ 4924 drv_usecwait(AHCI_1MS_USECS*2); 4925 4926 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 4927 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4928 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 4929 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 4930 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4931 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 4932 port_scontrol); 4933 } else { 4934 /* Do staggered spin-up */ 4935 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4936 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 4937 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 4938 4939 /* PxSCTL.DET must be 0 */ 4940 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4941 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 4942 port_scontrol); 4943 4944 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 4945 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4946 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4947 port_cmd_status); 4948 4949 /* 0 -> 1 edge */ 4950 drv_usecwait(AHCI_1MS_USECS*2); 4951 4952 /* Set PxCMD.SUD to 1 */ 4953 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4954 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4955 port_cmd_status |= AHCI_CMD_STATUS_SUD; 4956 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4957 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4958 port_cmd_status); 4959 4960 /* Enable PxCMD.FRE to read device */ 4961 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4962 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4963 port_cmd_status|AHCI_CMD_STATUS_FRE); 4964 } 4965 4966 /* 4967 * The port enters P:StartComm state, and HBA tells link layer to 4968 * start communication, which involves sending COMRESET to device. 4969 * And the HBA resets PxTFD.STS to 7Fh. 4970 * 4971 * When a COMINIT is received from the device, then the port enters 4972 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 4973 * PxSSTS.DET to 1h to indicate a device is detected but communication 4974 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 4975 * a COMINIT has been received. 4976 */ 4977 /* 4978 * The DET field is valid only if IPM field indicates 4979 * that the interface is in active state. 4980 */ 4981 loop_count = 0; 4982 do { 4983 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4984 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4985 4986 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 4987 /* 4988 * If the interface is not active, the DET field 4989 * is considered not accurate. So we want to 4990 * continue looping. 4991 */ 4992 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 4993 } 4994 4995 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 4996 /* 4997 * We are effectively timing out after 0.1 sec. 4998 */ 4999 break; 5000 } 5001 5002 /* Wait for 10 millisec */ 5003 drv_usecwait(AHCI_10MS_USECS); 5004 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 5005 5006 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5007 "ahci_port_reset: 1st loop count: %d, " 5008 "port_sstatus = 0x%x port %d", 5009 loop_count, port_sstatus, port); 5010 5011 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 5012 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 5013 /* 5014 * Either the port is not active or there 5015 * is no device present. 5016 */ 5017 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_NONE); 5018 return (AHCI_SUCCESS); 5019 } 5020 5021 /* Now we can make sure there is a device connected to the port */ 5022 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5023 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 5024 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5025 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5026 5027 /* 5028 * A COMINIT signal is supposed to be received 5029 * PxSERR.DIAG.X or PxIS.PCS should be set 5030 */ 5031 if (!(port_intr_status & AHCI_INTR_STATUS_PCS) && 5032 !(port_serror & SERROR_EXCHANGED_ERR)) { 5033 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 5034 "COMINIT signal from the device not received", 5035 instance, port); 5036 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_PSTATE_FAILED); 5037 return (AHCI_FAILURE); 5038 } 5039 5040 /* 5041 * According to the spec, when PxSCTL.DET is set to 0h, upon 5042 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 5043 * shall be set to '1' by the HBA. 5044 * 5045 * However, we found JMicron JMB363 doesn't follow this, so 5046 * remove this check, and just print a debug message. 5047 */ 5048 #if AHCI_DEBUG 5049 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5050 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5051 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 5052 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 5053 "port %d BSY bit is not set after COMINIT signal " 5054 "is received", port); 5055 } 5056 #endif 5057 5058 /* 5059 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 5060 * the D2H FIS received by HBA. 5061 */ 5062 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5063 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5064 SERROR_EXCHANGED_ERR); 5065 5066 /* 5067 * Devices should return a FIS contains its signature to HBA after 5068 * COMINIT signal. Check whether a D2H FIS is received by polling 5069 * PxTFD.STS.ERR bit. 5070 */ 5071 loop_count = 0; 5072 do { 5073 /* Wait for 10 millisec */ 5074 drv_usecwait(AHCI_10MS_USECS); 5075 5076 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 5077 /* 5078 * We are effectively timing out after 11 sec. 5079 */ 5080 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 5081 "the device hardware has been initialized and " 5082 "the power-up diagnostics failed", 5083 instance, port); 5084 5085 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 5086 "port %d PxTFD.STS.ERR is not set, we need another " 5087 "software reset.", port); 5088 5089 /* Clear port serror register for the port */ 5090 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5091 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5092 AHCI_SERROR_CLEAR_ALL); 5093 5094 AHCI_ADDR_SET_PMULT(&pmult_addr, port); 5095 5096 /* Try another software reset. */ 5097 if (ahci_software_reset(ahci_ctlp, ahci_portp, 5098 &pmult_addr) != AHCI_SUCCESS) { 5099 AHCIPORT_SET_STATE(ahci_portp, addrp, 5100 SATA_PSTATE_FAILED); 5101 return (AHCI_FAILURE); 5102 } 5103 break; 5104 } 5105 5106 /* Wait for 10 millisec */ 5107 drv_usecwait(AHCI_10MS_USECS); 5108 5109 /* 5110 * The Error bit '1' means COMRESET is finished successfully 5111 * The device hardware has been initialized and the power-up 5112 * diagnostics successfully completed. The device requests 5113 * that the Transport layer transmit a Register - D2H FIS to 5114 * the host. (SATA spec 11.5, v2.6) 5115 */ 5116 port_task_file = 5117 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5118 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5119 } while (((port_task_file & AHCI_TFD_ERR_MASK) 5120 >> AHCI_TFD_ERR_SHIFT) != AHCI_TFD_ERR_SGS); 5121 5122 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5123 "ahci_port_reset: 2nd loop count: %d, " 5124 "port_task_file = 0x%x port %d", 5125 loop_count, port_task_file, port); 5126 5127 /* Clear port serror register for the port */ 5128 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5129 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5130 AHCI_SERROR_CLEAR_ALL); 5131 5132 /* Set port as ready */ 5133 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp); 5134 AHCIPORT_SET_STATE(ahci_portp, addrp, port_state|SATA_STATE_READY); 5135 5136 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp, 5137 "ahci_port_reset: succeed at port %d.", port); 5138 return (AHCI_SUCCESS); 5139 } 5140 5141 /* 5142 * COMRESET on a port multiplier port. 5143 * 5144 * NOTE: Only called in ahci_port_reset() 5145 */ 5146 static int 5147 ahci_pmport_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5148 ahci_addr_t *addrp) 5149 { 5150 uint32_t port_scontrol, port_sstatus, port_serror; 5151 uint32_t port_cmd_status, port_intr_status; 5152 uint32_t port_state; 5153 uint8_t port = addrp->aa_port; 5154 uint8_t pmport = addrp->aa_pmport; 5155 int loop_count; 5156 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5157 5158 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 5159 "port %d:%d: pmport resetting", port, pmport); 5160 5161 /* Initialize pmport state */ 5162 AHCIPORT_SET_STATE(ahci_portp, addrp, 0); 5163 5164 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &port_scontrol, err); 5165 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 5166 WRITE_PMULT(addrp, SATA_PMULT_REG_SCTL, port_scontrol, err); 5167 5168 /* PxCMD.FRE should be set before. */ 5169 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5170 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5171 ASSERT(port_cmd_status & AHCI_CMD_STATUS_FRE); 5172 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) 5173 return (AHCI_FAILURE); 5174 5175 /* 5176 * Give time for COMRESET to percolate, according to the AHCI 5177 * spec, software shall wait at least 1 millisecond before 5178 * clearing PxSCTL.DET 5179 */ 5180 drv_usecwait(AHCI_1MS_USECS*2); 5181 5182 /* 5183 * Fetch the SCONTROL again and rewrite the DET part with 0 5184 * This will generate an Asychronous Notification events. 5185 */ 5186 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &port_scontrol, err); 5187 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 5188 WRITE_PMULT(addrp, SATA_PMULT_REG_SCTL, port_scontrol, err); 5189 5190 /* 5191 * The port enters P:StartComm state, and HBA tells link layer to 5192 * start communication, which involves sending COMRESET to device. 5193 * And the HBA resets PxTFD.STS to 7Fh. 5194 * 5195 * When a COMINIT is received from the device, then the port enters 5196 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 5197 * PxSSTS.DET to 1h to indicate a device is detected but communication 5198 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 5199 * a COMINIT has been received. 5200 */ 5201 /* 5202 * The DET field is valid only if IPM field indicates 5203 * that the interface is in active state. 5204 */ 5205 loop_count = 0; 5206 do { 5207 READ_PMULT(addrp, SATA_PMULT_REG_SSTS, &port_sstatus, err); 5208 5209 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 5210 /* 5211 * If the interface is not active, the DET field 5212 * is considered not accurate. So we want to 5213 * continue looping. 5214 */ 5215 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 5216 } 5217 5218 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 5219 /* 5220 * We are effectively timing out after 0.1 sec. 5221 */ 5222 break; 5223 } 5224 5225 /* Wait for 10 millisec */ 5226 drv_usecwait(AHCI_10MS_USECS); 5227 5228 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 5229 5230 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp, 5231 "ahci_pmport_reset: 1st loop count: %d, " 5232 "port_sstatus = 0x%x port %d:%d", 5233 loop_count, port_sstatus, port, pmport); 5234 5235 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 5236 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 5237 /* 5238 * Either the port is not active or there 5239 * is no device present. 5240 */ 5241 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 5242 "ahci_pmport_reset: " 5243 "no device attached to port %d:%d", 5244 port, pmport); 5245 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_NONE); 5246 return (AHCI_SUCCESS); 5247 } 5248 5249 /* Now we can make sure there is a device connected to the port */ 5250 /* COMINIT signal is supposed to be received (PxSERR.DIAG.X = '1') */ 5251 READ_PMULT(addrp, SATA_PMULT_REG_SERR, &port_serror, err); 5252 5253 if (!(port_serror & (1 << 26))) { 5254 cmn_err(CE_WARN, "!ahci%d: ahci_pmport_reset: " 5255 "COMINIT signal from the device not received port %d:%d", 5256 instance, port, pmport); 5257 5258 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_PSTATE_FAILED); 5259 return (AHCI_FAILURE); 5260 } 5261 5262 /* 5263 * After clear PxSERR register, we will receive a D2H FIS. 5264 * Normally this FIS will cause a IPMS error according to AHCI spec 5265 * v1.2 because there is no command outstanding for it. So we need 5266 * to ignore this error. 5267 */ 5268 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_IGNORE_IPMS; 5269 WRITE_PMULT(addrp, SATA_PMULT_REG_SERR, AHCI_SERROR_CLEAR_ALL, err); 5270 5271 /* Now we need to check the D2H FIS by checking IPMS error. */ 5272 loop_count = 0; 5273 do { 5274 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5275 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 5276 5277 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 5278 /* 5279 * No D2H FIS received. This is possible according 5280 * to SATA 2.6 spec. 5281 */ 5282 cmn_err(CE_WARN, "ahci_port_reset: port %d:%d " 5283 "PxIS.IPMS is not set, we need another " 5284 "software reset.", port, pmport); 5285 5286 break; 5287 } 5288 5289 /* Wait for 10 millisec */ 5290 mutex_exit(&ahci_portp->ahciport_mutex); 5291 delay(AHCI_10MS_TICKS); 5292 mutex_enter(&ahci_portp->ahciport_mutex); 5293 5294 } while (!(port_intr_status & AHCI_INTR_STATUS_IPMS)); 5295 5296 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp, 5297 "ahci_pmport_reset: 2st loop count: %d, " 5298 "port_sstatus = 0x%x port %d:%d", 5299 loop_count, port_sstatus, port, pmport); 5300 5301 /* Clear IPMS */ 5302 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5303 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5304 AHCI_INTR_STATUS_IPMS); 5305 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_IGNORE_IPMS; 5306 5307 /* This pmport is now ready for ahci_tran_start() */ 5308 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp); 5309 AHCIPORT_SET_STATE(ahci_portp, addrp, port_state|SATA_STATE_READY); 5310 5311 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp, 5312 "ahci_pmport_reset: succeed at port %d:%d", port, pmport); 5313 return (AHCI_SUCCESS); 5314 5315 err: /* R/W PMULT error */ 5316 /* IPMS flags might be set before. */ 5317 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_IGNORE_IPMS; 5318 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp, 5319 "ahci_pmport_reset: failed at port %d:%d", port, pmport); 5320 5321 return (AHCI_FAILURE); 5322 } 5323 5324 /* 5325 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 5326 * This is the most intrusive. 5327 * 5328 * When an HBA reset occurs, Phy communication will be re-established with 5329 * the device through a COMRESET followed by the normal out-of-band 5330 * communication sequence defined in Serial ATA. AT the end of reset, the 5331 * device, if working properly, will send a D2H Register FIS, which contains 5332 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 5333 * and PxTFD.ERR register fields, and updates the PxSIG register with the 5334 * signature. 5335 * 5336 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 5337 */ 5338 static int 5339 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 5340 { 5341 ahci_port_t *ahci_portp; 5342 ahci_addr_t addr; 5343 uint32_t ghc_control; 5344 uint8_t port; 5345 int loop_count; 5346 int rval = AHCI_SUCCESS; 5347 5348 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting", 5349 NULL); 5350 5351 mutex_enter(&ahci_ctlp->ahcictl_mutex); 5352 5353 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5354 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5355 5356 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 5357 ghc_control |= AHCI_HBA_GHC_HR; 5358 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5359 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5360 5361 /* 5362 * Wait until HBA Reset complete or timeout 5363 */ 5364 loop_count = 0; 5365 do { 5366 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5367 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5368 5369 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 5370 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5371 "ahci hba reset is timing out, " 5372 "ghc_control = 0x%x", ghc_control); 5373 /* We are effectively timing out after 1 sec. */ 5374 break; 5375 } 5376 5377 /* Wait for 10 millisec */ 5378 drv_usecwait(AHCI_10MS_USECS); 5379 } while (ghc_control & AHCI_HBA_GHC_HR); 5380 5381 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp, 5382 "ahci_hba_reset: 1st loop count: %d, " 5383 "ghc_control = 0x%x", loop_count, ghc_control); 5384 5385 if (ghc_control & AHCI_HBA_GHC_HR) { 5386 /* The hba is not reset for some reasons */ 5387 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5388 "hba reset failed: HBA in a hung or locked state", NULL); 5389 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5390 return (AHCI_FAILURE); 5391 } 5392 5393 /* 5394 * HBA reset will clear (AHCI Spec v1.2 10.4.3) GHC.IE / GHC.AE 5395 */ 5396 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5397 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5398 ghc_control |= (AHCI_HBA_GHC_AE | AHCI_HBA_GHC_IE); 5399 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5400 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5401 5402 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5403 5404 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 5405 /* Only check implemented ports */ 5406 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 5407 continue; 5408 } 5409 5410 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 5411 mutex_enter(&ahci_portp->ahciport_mutex); 5412 5413 AHCI_ADDR_SET_PORT(&addr, port); 5414 5415 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 5416 port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, NULL) != 5417 AHCI_SUCCESS) { 5418 rval = AHCI_FAILURE; 5419 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 5420 "ahci_hba_reset: port %d failed", port); 5421 /* 5422 * Set the port state to SATA_PSTATE_FAILED if 5423 * failed to initialize it. 5424 */ 5425 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 5426 } 5427 5428 mutex_exit(&ahci_portp->ahciport_mutex); 5429 } 5430 5431 return (rval); 5432 } 5433 5434 /* 5435 * This routine is only called from AHCI_ATTACH or phyrdy change 5436 * case. It first calls software reset, then stop the port and try to 5437 * read PxSIG register to find the type of device attached to the port. 5438 * 5439 * The caller should make sure a valid device exists on specified port and 5440 * physical communication has been established so that the signature could 5441 * be retrieved by software reset. 5442 * 5443 * WARNING!!! ahciport_mutex should be acquired before the function 5444 * is called. And the port interrupt is disabled. 5445 */ 5446 static void 5447 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5448 ahci_addr_t *addrp) 5449 { 5450 ahci_addr_t dev_addr; 5451 uint32_t signature; 5452 uint8_t port = addrp->aa_port; 5453 uint8_t pmport = addrp->aa_pmport; 5454 int rval; 5455 5456 ASSERT(AHCI_ADDR_IS_VALID(addrp)); 5457 5458 /* 5459 * If the HBA doesn't support port multiplier, then the driver 5460 * doesn't need to bother to check port multiplier device. 5461 * 5462 * The second port of ICH7 on ASUS P5W DH deluxe motherboard is 5463 * connected to Silicon Image 4723, to which the two sata drives 5464 * attached can be set with RAID1, RAID0 or Spanning mode. 5465 * 5466 * We found software reset will get failure if port multiplier address 5467 * 0xf is used by software reset, so just ignore the check since 5468 * ICH7 doesn't support port multiplier device at all. 5469 */ 5470 if (AHCI_ADDR_IS_PORT(addrp) && 5471 (ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_CBSS)) { 5472 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 5473 "ahci_find_dev_signature enter: port %d", port); 5474 5475 /* 5476 * NOTE: when the ahci address is a HBA port, we do not know 5477 * it is a device or a port multiplier that attached. we need 5478 * try a software reset at port multiplier address (0xf 5479 * pmport) 5480 */ 5481 AHCI_ADDR_SET_PMULT(&dev_addr, addrp->aa_port); 5482 } else { 5483 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 5484 "ahci_find_dev_signature enter: port %d:%d", 5485 port, pmport); 5486 dev_addr = *addrp; 5487 } 5488 5489 /* Assume it is unknown. */ 5490 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN); 5491 5492 /* Issue a software reset to get the signature */ 5493 rval = ahci_software_reset(ahci_ctlp, ahci_portp, &dev_addr); 5494 if (rval != AHCI_SUCCESS) { 5495 5496 /* 5497 * Try to do software reset again with pmport set with 0 if 5498 * the controller is set with AHCI_CAP_SRST_NO_HOSTPORT and 5499 * the original pmport is set with SATA_PMULT_HOSTPORT (0xf) 5500 */ 5501 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_SRST_NO_HOSTPORT) && 5502 (dev_addr.aa_pmport == SATA_PMULT_HOSTPORT)) { 5503 dev_addr.aa_pmport = 0; 5504 rval = ahci_software_reset(ahci_ctlp, ahci_portp, 5505 &dev_addr); 5506 } 5507 5508 if (rval != AHCI_SUCCESS) { 5509 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 5510 "ahci_find_dev_signature: software reset failed " 5511 "at port %d:%d, cannot get signature.", 5512 port, pmport); 5513 5514 AHCIPORT_SET_STATE(ahci_portp, addrp, 5515 SATA_PSTATE_FAILED); 5516 return; 5517 } 5518 } 5519 5520 /* 5521 * ahci_software_reset has started the port, so we need manually stop 5522 * the port again. 5523 */ 5524 if (AHCI_ADDR_IS_PORT(addrp)) { 5525 if (ahci_put_port_into_notrunning_state(ahci_ctlp, 5526 ahci_portp, port) != AHCI_SUCCESS) { 5527 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 5528 "ahci_find_dev_signature: cannot stop port %d.", 5529 port); 5530 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 5531 return; 5532 } 5533 } 5534 5535 /* Now we can make sure that a valid signature is received. */ 5536 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5537 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 5538 5539 #ifdef AHCI_DEBUG 5540 if (AHCI_ADDR_IS_PMPORT(addrp)) { 5541 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 5542 "ahci_find_dev_signature: signature = 0x%x at port %d:%d", 5543 signature, port, pmport); 5544 } else { 5545 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 5546 "ahci_find_dev_signature: signature = 0x%x at port %d", 5547 signature, port); 5548 } 5549 #endif 5550 5551 /* NOTE: Only support ATAPI device at controller port. */ 5552 if (signature == AHCI_SIGNATURE_ATAPI && !AHCI_ADDR_IS_PORT(addrp)) 5553 signature = SATA_DTYPE_UNKNOWN; 5554 5555 switch (signature) { 5556 5557 case AHCI_SIGNATURE_DISK: 5558 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_ATADISK); 5559 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 5560 "Disk is found at port: %d", port); 5561 break; 5562 5563 case AHCI_SIGNATURE_ATAPI: 5564 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_ATAPI); 5565 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 5566 "ATAPI device is found at port: %d", port); 5567 break; 5568 5569 case AHCI_SIGNATURE_PORT_MULTIPLIER: 5570 /* Port Multiplier cannot recursively attached. */ 5571 ASSERT(AHCI_ADDR_IS_PORT(addrp)); 5572 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_PMULT); 5573 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 5574 "Port Multiplier is found at port: %d", port); 5575 break; 5576 5577 default: 5578 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN); 5579 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 5580 "Unknown device is found at port: %d", port); 5581 } 5582 } 5583 5584 /* 5585 * According to the spec, to reliably detect hot plug removals, software 5586 * must disable interface power management. Software should perform the 5587 * following initialization on a port after a device is attached: 5588 * Set PxSCTL.IPM to 3h to disable interface state transitions 5589 * Set PxCMD.ALPE to '0' to disable aggressive power management 5590 * Disable device initiated interface power management by SET FEATURE 5591 * 5592 * We can ignore the last item because by default the feature is disabled 5593 */ 5594 static void 5595 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 5596 { 5597 uint32_t port_scontrol, port_cmd_status; 5598 5599 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5600 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 5601 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 5602 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5603 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 5604 5605 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5606 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5607 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 5608 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5609 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5610 } 5611 5612 /* 5613 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 5614 * to 1, then set it firstly. 5615 * 5616 * Each port contains two major DMA engines. One DMA engine walks through 5617 * the command list, and is controlled by PxCMD.ST. The second DMA engine 5618 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 5619 * 5620 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 5621 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 5622 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 5623 * 5624 * Software shall not set PxCMD.ST to '1' unless a functional device is 5625 * present on the port(as determined by PxTFD.STS.BSY = '0', 5626 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 5627 * 5628 * WARNING!!! ahciport_mutex should be acquired before the function 5629 * is called. 5630 */ 5631 static int 5632 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 5633 { 5634 uint32_t port_cmd_status; 5635 5636 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 5637 5638 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 5639 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 5640 "the state for port %d is 0x%x", 5641 port, ahci_portp->ahciport_port_state); 5642 return (AHCI_FAILURE); 5643 } 5644 5645 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5646 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 5647 "no device is attached at port %d", port); 5648 return (AHCI_FAILURE); 5649 } 5650 5651 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 5652 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5653 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5654 5655 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 5656 port_cmd_status |= AHCI_CMD_STATUS_FRE; 5657 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5658 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 5659 port_cmd_status); 5660 } 5661 5662 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5663 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5664 5665 port_cmd_status |= AHCI_CMD_STATUS_ST; 5666 5667 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5668 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 5669 port_cmd_status); 5670 5671 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 5672 5673 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port: " 5674 "PxCMD.ST set to '1' at port %d", port); 5675 5676 return (AHCI_SUCCESS); 5677 } 5678 5679 /* 5680 * Allocate the ahci_port_t including Received FIS and Command List. 5681 * The argument - port is the physical port number, and not logical 5682 * port number seen by the SATA framework. 5683 * 5684 * WARNING!!! ahcictl_mutex should be acquired before the function 5685 * is called. 5686 */ 5687 static int 5688 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 5689 { 5690 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5691 ahci_port_t *ahci_portp; 5692 char taskq_name[64] = "event_handle_taskq"; 5693 5694 ahci_portp = 5695 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 5696 5697 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 5698 ahci_portp->ahciport_port_num = port; 5699 5700 /* Initialize the port condition variable */ 5701 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 5702 5703 /* Initialize the port mutex */ 5704 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 5705 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 5706 5707 mutex_enter(&ahci_portp->ahciport_mutex); 5708 5709 /* 5710 * Allocate memory for received FIS structure and 5711 * command list for this port 5712 */ 5713 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 5714 goto err_case1; 5715 } 5716 5717 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 5718 goto err_case2; 5719 } 5720 5721 (void) snprintf(taskq_name + strlen(taskq_name), 5722 sizeof (taskq_name) - strlen(taskq_name), 5723 "_port%d", port); 5724 5725 /* Create the taskq for the port */ 5726 if ((ahci_portp->ahciport_event_taskq = ddi_taskq_create(dip, 5727 taskq_name, 2, TASKQ_DEFAULTPRI, 0)) == NULL) { 5728 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 5729 "handle", ddi_get_instance(ahci_ctlp->ahcictl_dip)); 5730 goto err_case3; 5731 } 5732 5733 /* Allocate the argument for the taskq */ 5734 ahci_portp->ahciport_event_args = 5735 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 5736 5737 ahci_portp->ahciport_event_args->ahciea_addrp = 5738 kmem_zalloc(sizeof (ahci_addr_t), KM_SLEEP); 5739 5740 if (ahci_portp->ahciport_event_args == NULL) 5741 goto err_case4; 5742 5743 mutex_exit(&ahci_portp->ahciport_mutex); 5744 5745 return (AHCI_SUCCESS); 5746 5747 err_case4: 5748 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq); 5749 5750 err_case3: 5751 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 5752 5753 err_case2: 5754 ahci_dealloc_rcvd_fis(ahci_portp); 5755 5756 err_case1: 5757 mutex_exit(&ahci_portp->ahciport_mutex); 5758 mutex_destroy(&ahci_portp->ahciport_mutex); 5759 cv_destroy(&ahci_portp->ahciport_cv); 5760 5761 kmem_free(ahci_portp, sizeof (ahci_port_t)); 5762 5763 return (AHCI_FAILURE); 5764 } 5765 5766 /* 5767 * Reverse of ahci_dealloc_port_state(). 5768 * 5769 * WARNING!!! ahcictl_mutex should be acquired before the function 5770 * is called. 5771 */ 5772 static void 5773 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 5774 { 5775 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 5776 5777 ASSERT(ahci_portp != NULL); 5778 5779 mutex_enter(&ahci_portp->ahciport_mutex); 5780 kmem_free(ahci_portp->ahciport_event_args->ahciea_addrp, 5781 sizeof (ahci_addr_t)); 5782 ahci_portp->ahciport_event_args->ahciea_addrp = NULL; 5783 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 5784 ahci_portp->ahciport_event_args = NULL; 5785 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq); 5786 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 5787 ahci_dealloc_rcvd_fis(ahci_portp); 5788 ahci_dealloc_pmult(ahci_ctlp, ahci_portp); 5789 mutex_exit(&ahci_portp->ahciport_mutex); 5790 5791 mutex_destroy(&ahci_portp->ahciport_mutex); 5792 cv_destroy(&ahci_portp->ahciport_cv); 5793 5794 kmem_free(ahci_portp, sizeof (ahci_port_t)); 5795 5796 ahci_ctlp->ahcictl_ports[port] = NULL; 5797 } 5798 5799 /* 5800 * Allocates memory for the Received FIS Structure 5801 * 5802 * WARNING!!! ahciport_mutex should be acquired before the function 5803 * is called. 5804 */ 5805 static int 5806 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5807 uint8_t port) 5808 { 5809 size_t rcvd_fis_size; 5810 size_t ret_len; 5811 uint_t cookie_count; 5812 5813 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 5814 5815 /* allocate rcvd FIS dma handle. */ 5816 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 5817 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 5818 DDI_DMA_SLEEP, 5819 NULL, 5820 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 5821 DDI_SUCCESS) { 5822 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5823 "rcvd FIS dma handle alloc failed", NULL); 5824 5825 return (AHCI_FAILURE); 5826 } 5827 5828 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 5829 rcvd_fis_size, 5830 &accattr, 5831 DDI_DMA_CONSISTENT, 5832 DDI_DMA_SLEEP, 5833 NULL, 5834 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 5835 &ret_len, 5836 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 5837 5838 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5839 "rcvd FIS dma mem alloc fail", NULL); 5840 /* error.. free the dma handle. */ 5841 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 5842 return (AHCI_FAILURE); 5843 } 5844 5845 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 5846 NULL, 5847 (caddr_t)ahci_portp->ahciport_rcvd_fis, 5848 rcvd_fis_size, 5849 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 5850 DDI_DMA_SLEEP, 5851 NULL, 5852 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 5853 &cookie_count) != DDI_DMA_MAPPED) { 5854 5855 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5856 "rcvd FIS dma handle bind fail", NULL); 5857 /* error.. free the dma handle & free the memory. */ 5858 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 5859 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 5860 return (AHCI_FAILURE); 5861 } 5862 5863 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 5864 5865 /* Config Port Received FIS Base Address */ 5866 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 5867 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 5868 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 5869 5870 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 5871 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 5872 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 5873 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 5874 5875 return (AHCI_SUCCESS); 5876 } 5877 5878 /* 5879 * Deallocates the Received FIS Structure 5880 * 5881 * WARNING!!! ahciport_mutex should be acquired before the function 5882 * is called. 5883 */ 5884 static void 5885 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 5886 { 5887 /* Unbind the cmd list dma handle first. */ 5888 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 5889 5890 /* Then free the underlying memory. */ 5891 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 5892 5893 /* Now free the handle itself. */ 5894 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 5895 } 5896 5897 /* 5898 * Allocates memory for the Command List, which contains up to 32 entries. 5899 * Each entry contains a command header, which is a 32-byte structure that 5900 * includes the pointer to the command table. 5901 * 5902 * WARNING!!! ahciport_mutex should be acquired before the function 5903 * is called. 5904 */ 5905 static int 5906 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5907 uint8_t port) 5908 { 5909 size_t cmd_list_size; 5910 size_t ret_len; 5911 uint_t cookie_count; 5912 5913 cmd_list_size = 5914 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 5915 5916 /* allocate cmd list dma handle. */ 5917 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 5918 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 5919 DDI_DMA_SLEEP, 5920 NULL, 5921 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 5922 5923 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5924 "cmd list dma handle alloc failed", NULL); 5925 return (AHCI_FAILURE); 5926 } 5927 5928 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 5929 cmd_list_size, 5930 &accattr, 5931 DDI_DMA_CONSISTENT, 5932 DDI_DMA_SLEEP, 5933 NULL, 5934 (caddr_t *)&ahci_portp->ahciport_cmd_list, 5935 &ret_len, 5936 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 5937 5938 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5939 "cmd list dma mem alloc fail", NULL); 5940 /* error.. free the dma handle. */ 5941 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 5942 return (AHCI_FAILURE); 5943 } 5944 5945 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 5946 NULL, 5947 (caddr_t)ahci_portp->ahciport_cmd_list, 5948 cmd_list_size, 5949 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 5950 DDI_DMA_SLEEP, 5951 NULL, 5952 &ahci_portp->ahciport_cmd_list_dma_cookie, 5953 &cookie_count) != DDI_DMA_MAPPED) { 5954 5955 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 5956 "cmd list dma handle bind fail", NULL); 5957 /* error.. free the dma handle & free the memory. */ 5958 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 5959 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 5960 return (AHCI_FAILURE); 5961 } 5962 5963 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 5964 5965 /* Config Port Command List Base Address */ 5966 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 5967 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 5968 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 5969 5970 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 5971 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 5972 5973 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 5974 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 5975 5976 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 5977 goto err_out; 5978 } 5979 5980 return (AHCI_SUCCESS); 5981 5982 err_out: 5983 /* Unbind the cmd list dma handle first. */ 5984 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 5985 5986 /* Then free the underlying memory. */ 5987 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 5988 5989 /* Now free the handle itself. */ 5990 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 5991 5992 return (AHCI_FAILURE); 5993 } 5994 5995 /* 5996 * Deallocates the Command List 5997 * 5998 * WARNING!!! ahciport_mutex should be acquired before the function 5999 * is called. 6000 */ 6001 static void 6002 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 6003 { 6004 /* First dealloc command table */ 6005 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 6006 6007 /* Unbind the cmd list dma handle first. */ 6008 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 6009 6010 /* Then free the underlying memory. */ 6011 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 6012 6013 /* Now free the handle itself. */ 6014 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 6015 } 6016 6017 /* 6018 * Allocates memory for all Command Tables, which contains Command FIS, 6019 * ATAPI Command and Physical Region Descriptor Table. 6020 * 6021 * WARNING!!! ahciport_mutex should be acquired before the function 6022 * is called. 6023 */ 6024 static int 6025 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 6026 { 6027 size_t ret_len; 6028 ddi_dma_cookie_t cmd_table_dma_cookie; 6029 uint_t cookie_count; 6030 int slot; 6031 6032 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 6033 "ahci_alloc_cmd_tables: port %d enter", 6034 ahci_portp->ahciport_port_num); 6035 6036 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 6037 /* Allocate cmd table dma handle. */ 6038 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 6039 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 6040 DDI_DMA_SLEEP, 6041 NULL, 6042 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 6043 DDI_SUCCESS) { 6044 6045 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 6046 "cmd table dma handle alloc failed", NULL); 6047 6048 goto err_out; 6049 } 6050 6051 if (ddi_dma_mem_alloc( 6052 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 6053 ahci_cmd_table_size, 6054 &accattr, 6055 DDI_DMA_CONSISTENT, 6056 DDI_DMA_SLEEP, 6057 NULL, 6058 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 6059 &ret_len, 6060 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 6061 NULL) { 6062 6063 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 6064 "cmd table dma mem alloc fail", NULL); 6065 6066 /* error.. free the dma handle. */ 6067 ddi_dma_free_handle( 6068 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 6069 goto err_out; 6070 } 6071 6072 if (ddi_dma_addr_bind_handle( 6073 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 6074 NULL, 6075 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 6076 ahci_cmd_table_size, 6077 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 6078 DDI_DMA_SLEEP, 6079 NULL, 6080 &cmd_table_dma_cookie, 6081 &cookie_count) != DDI_DMA_MAPPED) { 6082 6083 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 6084 "cmd table dma handle bind fail", NULL); 6085 /* error.. free the dma handle & free the memory. */ 6086 ddi_dma_mem_free( 6087 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 6088 ddi_dma_free_handle( 6089 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 6090 goto err_out; 6091 } 6092 6093 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 6094 ahci_cmd_table_size); 6095 6096 /* Config Port Command Table Base Address */ 6097 SET_COMMAND_TABLE_BASE_ADDR( 6098 (&ahci_portp->ahciport_cmd_list[slot]), 6099 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 6100 6101 #ifndef __lock_lint 6102 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 6103 (&ahci_portp->ahciport_cmd_list[slot]), 6104 cmd_table_dma_cookie.dmac_laddress >> 32); 6105 #endif 6106 } 6107 6108 return (AHCI_SUCCESS); 6109 err_out: 6110 6111 for (slot--; slot >= 0; slot--) { 6112 /* Unbind the cmd table dma handle first */ 6113 (void) ddi_dma_unbind_handle( 6114 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 6115 6116 /* Then free the underlying memory */ 6117 ddi_dma_mem_free( 6118 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 6119 6120 /* Now free the handle itself */ 6121 ddi_dma_free_handle( 6122 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 6123 } 6124 6125 return (AHCI_FAILURE); 6126 } 6127 6128 /* 6129 * Deallocates memory for all Command Tables. 6130 * 6131 * WARNING!!! ahciport_mutex should be acquired before the function 6132 * is called. 6133 */ 6134 static void 6135 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 6136 { 6137 int slot; 6138 6139 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 6140 "ahci_dealloc_cmd_tables: %d enter", 6141 ahci_portp->ahciport_port_num); 6142 6143 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 6144 /* Unbind the cmd table dma handle first. */ 6145 (void) ddi_dma_unbind_handle( 6146 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 6147 6148 /* Then free the underlying memory. */ 6149 ddi_dma_mem_free( 6150 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 6151 6152 /* Now free the handle itself. */ 6153 ddi_dma_free_handle( 6154 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 6155 } 6156 } 6157 6158 /* 6159 * Update SATA registers at controller ports 6160 * 6161 * WARNING!!! ahciport_mutex should be acquired before those functions 6162 * get called. 6163 */ 6164 static void 6165 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 6166 sata_device_t *sd) 6167 { 6168 sd->satadev_scr.sstatus = 6169 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6170 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 6171 sd->satadev_scr.serror = 6172 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6173 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 6174 sd->satadev_scr.scontrol = 6175 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6176 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 6177 sd->satadev_scr.sactive = 6178 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6179 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 6180 } 6181 6182 /* 6183 * For poll mode, ahci_port_intr will be called to emulate the interrupt 6184 */ 6185 static void 6186 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 6187 { 6188 uint32_t port_intr_status; 6189 uint32_t port_intr_enable; 6190 6191 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 6192 "ahci_port_intr enter: port %d", port); 6193 6194 mutex_enter(&ahci_portp->ahciport_mutex); 6195 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 6196 /* For SATA_OPMODE_POLLING commands */ 6197 port_intr_enable = 6198 (AHCI_INTR_STATUS_DHRS | 6199 AHCI_INTR_STATUS_PSS | 6200 AHCI_INTR_STATUS_SDBS | 6201 AHCI_INTR_STATUS_UFS | 6202 AHCI_INTR_STATUS_PCS | 6203 AHCI_INTR_STATUS_PRCS | 6204 AHCI_INTR_STATUS_OFS | 6205 AHCI_INTR_STATUS_INFS | 6206 AHCI_INTR_STATUS_IFS | 6207 AHCI_INTR_STATUS_HBDS | 6208 AHCI_INTR_STATUS_HBFS | 6209 AHCI_INTR_STATUS_TFES); 6210 } else { 6211 /* 6212 * port_intr_enable indicates that the corresponding interrrupt 6213 * reporting is enabled. 6214 */ 6215 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6216 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 6217 } 6218 6219 /* IPMS error in port reset should be ignored according AHCI spec. */ 6220 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_IGNORE_IPMS)) 6221 port_intr_enable |= AHCI_INTR_STATUS_IPMS; 6222 mutex_exit(&ahci_portp->ahciport_mutex); 6223 6224 /* 6225 * port_intr_stats indicates that the corresponding interrupt 6226 * condition is active. 6227 */ 6228 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6229 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 6230 6231 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6232 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 6233 "port_intr_enable = 0x%x", 6234 port, port_intr_status, port_intr_enable); 6235 6236 port_intr_status &= port_intr_enable; 6237 6238 /* First clear the port interrupts status */ 6239 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6240 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 6241 port_intr_status); 6242 6243 /* Check the completed non-queued commands */ 6244 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 6245 AHCI_INTR_STATUS_PSS)) { 6246 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 6247 ahci_portp, port); 6248 } 6249 6250 /* Check the completed queued commands */ 6251 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 6252 (void) ahci_intr_set_device_bits(ahci_ctlp, 6253 ahci_portp, port); 6254 } 6255 6256 /* Check the port connect change status interrupt bit */ 6257 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 6258 (void) ahci_intr_port_connect_change(ahci_ctlp, 6259 ahci_portp, port); 6260 } 6261 6262 /* Check the device mechanical presence status interrupt bit */ 6263 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 6264 (void) ahci_intr_device_mechanical_presence_status( 6265 ahci_ctlp, ahci_portp, port); 6266 } 6267 6268 /* Check the PhyRdy change status interrupt bit */ 6269 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 6270 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 6271 port); 6272 } 6273 6274 /* 6275 * Check the non-fatal error interrupt bits, there are four 6276 * kinds of non-fatal errors at the time being: 6277 * 6278 * PxIS.UFS - Unknown FIS Error 6279 * PxIS.OFS - Overflow Error 6280 * PxIS.INFS - Interface Non-Fatal Error 6281 * PxIS.IPMS - Incorrect Port Multiplier Status Error 6282 * 6283 * For these non-fatal errors, the HBA can continue to operate, 6284 * so the driver just log the error messages. 6285 */ 6286 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 6287 AHCI_INTR_STATUS_OFS | 6288 AHCI_INTR_STATUS_IPMS | 6289 AHCI_INTR_STATUS_INFS)) { 6290 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 6291 port, port_intr_status); 6292 } 6293 6294 /* 6295 * Check the fatal error interrupt bits, there are four kinds 6296 * of fatal errors for AHCI controllers: 6297 * 6298 * PxIS.HBFS - Host Bus Fatal Error 6299 * PxIS.HBDS - Host Bus Data Error 6300 * PxIS.IFS - Interface Fatal Error 6301 * PxIS.TFES - Task File Error 6302 * 6303 * The fatal error means the HBA can not recover from it by 6304 * itself, and it will try to abort the transfer, and the software 6305 * must intervene to restart the port. 6306 */ 6307 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 6308 AHCI_INTR_STATUS_HBDS | 6309 AHCI_INTR_STATUS_HBFS | 6310 AHCI_INTR_STATUS_TFES)) 6311 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 6312 port, port_intr_status); 6313 6314 /* Check the cold port detect interrupt bit */ 6315 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 6316 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 6317 } 6318 6319 /* Second clear the corresponding bit in IS.IPS */ 6320 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6321 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 6322 } 6323 6324 /* 6325 * Interrupt service handler 6326 */ 6327 static uint_t 6328 ahci_intr(caddr_t arg1, caddr_t arg2) 6329 { 6330 #ifndef __lock_lint 6331 _NOTE(ARGUNUSED(arg2)) 6332 #endif 6333 /* LINTED */ 6334 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 6335 ahci_port_t *ahci_portp; 6336 int32_t global_intr_status; 6337 uint8_t port; 6338 6339 /* 6340 * global_intr_status indicates that the corresponding port has 6341 * an interrupt pending. 6342 */ 6343 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6344 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 6345 6346 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 6347 /* The interrupt is not ours */ 6348 return (DDI_INTR_UNCLAIMED); 6349 } 6350 6351 /* Loop for all the ports */ 6352 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6353 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6354 continue; 6355 } 6356 if (!((0x1 << port) & global_intr_status)) { 6357 continue; 6358 } 6359 6360 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6361 6362 /* Call ahci_port_intr */ 6363 ahci_port_intr(ahci_ctlp, ahci_portp, port); 6364 } 6365 6366 return (DDI_INTR_CLAIMED); 6367 } 6368 6369 /* 6370 * For non-queued commands, when the corresponding bit in the PxCI register 6371 * is cleared, it means the command is completed successfully. And according 6372 * to the HBA state machine, there are three conditions which possibly will 6373 * try to clear the PxCI register bit. 6374 * 1. Receive one D2H Register FIS which is with 'I' bit set 6375 * 2. Update PIO Setup FIS 6376 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 6377 * 6378 * Process completed non-queued commands when the interrupt status bit - 6379 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 6380 * 6381 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 6382 * with the 'I' bit set. And the following commands will send thus 6383 * FIS with 'I' bit set upon the successful completion: 6384 * 1. Non-data commands 6385 * 2. DMA data-in command 6386 * 3. DMA data-out command 6387 * 4. PIO data-out command 6388 * 5. PACKET non-data commands 6389 * 6. PACKET PIO data-in command 6390 * 7. PACKET PIO data-out command 6391 * 8. PACKET DMA data-in command 6392 * 9. PACKET DMA data-out command 6393 * 6394 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 6395 * with the 'I' bit set. And the following commands will send this 6396 * FIS upon the successful completion: 6397 * 1. PIO data-in command 6398 */ 6399 static int 6400 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 6401 ahci_port_t *ahci_portp, uint8_t port) 6402 { 6403 uint32_t port_cmd_issue = 0; 6404 uint32_t finished_tags; 6405 int finished_slot; 6406 sata_pkt_t *satapkt; 6407 ahci_fis_d2h_register_t *rcvd_fisp; 6408 #if AHCI_DEBUG 6409 ahci_cmd_header_t *cmd_header; 6410 uint32_t cmd_dmacount; 6411 #endif 6412 6413 mutex_enter(&ahci_portp->ahciport_mutex); 6414 6415 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 6416 !RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) && 6417 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6418 /* 6419 * Spurious interrupt. Nothing to be done. 6420 */ 6421 mutex_exit(&ahci_portp->ahciport_mutex); 6422 return (AHCI_SUCCESS); 6423 } 6424 6425 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6426 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6427 6428 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6429 /* Slot 0 is always used during error recovery */ 6430 finished_tags = 0x1 & ~port_cmd_issue; 6431 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 6432 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 6433 "retrieval is finished, and finished_tags = 0x%x", 6434 port, finished_tags); 6435 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) { 6436 finished_tags = 0x1 & ~port_cmd_issue; 6437 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, 6438 "ahci_intr_cmd_cmplt: port %d the sata pkt for r/w " 6439 "port multiplier is finished, and finished_tags = 0x%x", 6440 port, finished_tags); 6441 6442 } else { 6443 6444 finished_tags = ahci_portp->ahciport_pending_tags & 6445 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 6446 } 6447 6448 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6449 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 6450 "port_cmd_issue = 0x%x finished_tags = 0x%x", 6451 ahci_portp->ahciport_pending_tags, port_cmd_issue, 6452 finished_tags); 6453 6454 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 6455 (finished_tags == 0x1)) { 6456 satapkt = ahci_portp->ahciport_err_retri_pkt; 6457 ASSERT(satapkt != NULL); 6458 6459 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6460 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 6461 "with SATA_PKT_COMPLETED", (void *)satapkt); 6462 6463 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6464 goto out; 6465 } 6466 6467 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) && 6468 (finished_tags == 0x1)) { 6469 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt; 6470 ASSERT(satapkt != NULL); 6471 6472 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6473 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 6474 "with SATA_PKT_COMPLETED", (void *)satapkt); 6475 6476 /* READ PORTMULT need copy out FIS content. */ 6477 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6478 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6479 ahcirf_d2h_register_fis); 6480 satapkt->satapkt_cmd.satacmd_status_reg = 6481 GET_RFIS_STATUS(rcvd_fisp); 6482 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 6483 } 6484 6485 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6486 goto out; 6487 } 6488 6489 while (finished_tags) { 6490 finished_slot = ddi_ffs(finished_tags) - 1; 6491 if (finished_slot == -1) { 6492 goto out; 6493 } 6494 6495 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 6496 ASSERT(satapkt != NULL); 6497 #if AHCI_DEBUG 6498 /* 6499 * For non-native queued commands, the PRD byte count field 6500 * shall contain an accurate count of the number of bytes 6501 * transferred for the command before the PxCI bit is cleared 6502 * to '0' for the command. 6503 * 6504 * The purpose of this field is to let software know how many 6505 * bytes transferred for a given operation in order to 6506 * determine if underflow occurred. When issuing native command 6507 * queuing commands, this field should not be used and is not 6508 * required to be valid since in this case underflow is always 6509 * illegal. 6510 * 6511 * For data reads, the HBA will update its PRD byte count with 6512 * the total number of bytes received from the last FIS, and 6513 * may be able to continue normally. For data writes, the 6514 * device will detect an error, and HBA most likely will get 6515 * a fatal error. 6516 * 6517 * Therefore, here just put code to debug part. And please 6518 * refer to the comment above ahci_intr_fatal_error for the 6519 * definition of underflow error. 6520 */ 6521 cmd_dmacount = 6522 ahci_portp->ahciport_prd_bytecounts[finished_slot]; 6523 if (cmd_dmacount) { 6524 cmd_header = 6525 &ahci_portp->ahciport_cmd_list[finished_slot]; 6526 AHCIDBG(AHCIDBG_INTR|AHCIDBG_PRDT, ahci_ctlp, 6527 "ahci_intr_cmd_cmplt: port %d, " 6528 "PRD Byte Count = 0x%x, " 6529 "ahciport_prd_bytecounts = 0x%x", port, 6530 cmd_header->ahcich_prd_byte_count, 6531 cmd_dmacount); 6532 6533 if (cmd_header->ahcich_prd_byte_count != cmd_dmacount) { 6534 AHCIDBG(AHCIDBG_UNDERFLOW, ahci_ctlp, 6535 "ahci_intr_cmd_cmplt: port %d, " 6536 "an underflow occurred", port); 6537 } 6538 } 6539 #endif 6540 6541 /* 6542 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 6543 * feature, sata_special_regs flag will be set, and the 6544 * driver should copy the status and the other corresponding 6545 * register values in the D2H Register FIS received (It's 6546 * working on Non-data protocol) from the device back to 6547 * the sata_cmd. 6548 * 6549 * For every AHCI port, there is only one Received FIS 6550 * structure, which contains the FISes received from the 6551 * device, So we're trying to copy the content of D2H 6552 * Register FIS in the Received FIS structure back to 6553 * the sata_cmd. 6554 */ 6555 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6556 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6557 ahcirf_d2h_register_fis); 6558 satapkt->satapkt_cmd.satacmd_status_reg = 6559 GET_RFIS_STATUS(rcvd_fisp); 6560 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 6561 } 6562 6563 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6564 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 6565 "with SATA_PKT_COMPLETED", (void *)satapkt); 6566 6567 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 6568 CLEAR_BIT(finished_tags, finished_slot); 6569 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 6570 6571 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6572 } 6573 out: 6574 AHCIDBG(AHCIDBG_PKTCOMP, ahci_ctlp, 6575 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 6576 ahci_portp->ahciport_pending_tags); 6577 6578 mutex_exit(&ahci_portp->ahciport_mutex); 6579 6580 return (AHCI_SUCCESS); 6581 } 6582 6583 /* 6584 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 6585 * with the 'I' bit set and has been copied into system memory. It will 6586 * be sent under the following situations: 6587 * 6588 * 1. NCQ command is completed 6589 * 6590 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 6591 * via the Set Device Bits FIS. When such event is generated, the software 6592 * needs to read PxSACT register and compares the current value to the 6593 * list of commands previously issue by software. ahciport_pending_ncq_tags 6594 * keeps the tags of previously issued commands. 6595 * 6596 * 2. Asynchronous Notification 6597 * 6598 * Asynchronous Notification is a feature in SATA spec 2.6. 6599 * 6600 * 1) ATAPI device will send a signal to the host when media is inserted or 6601 * removed and avoids polling the device for media changes. The signal 6602 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 6603 * set to '1'. At the moment, it's not supported yet. 6604 * 6605 * 2) Port multiplier will send a signal to the host when a hot plug event 6606 * has occured on a port multiplier port. It is used when command based 6607 * switching is employed. This is handled by ahci_intr_pmult_sntf_events() 6608 */ 6609 static int 6610 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 6611 ahci_port_t *ahci_portp, uint8_t port) 6612 { 6613 ahci_addr_t addr; 6614 6615 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6616 "ahci_intr_set_device_bits enter: port %d", port); 6617 6618 /* Initialize HBA port address */ 6619 AHCI_ADDR_SET_PORT(&addr, port); 6620 6621 /* NCQ plug handler */ 6622 (void) ahci_intr_ncq_events(ahci_ctlp, ahci_portp, &addr); 6623 6624 /* Check port multiplier's asynchronous notification events */ 6625 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SNTF) { 6626 (void) ahci_intr_pmult_sntf_events(ahci_ctlp, 6627 ahci_portp, port); 6628 } 6629 6630 /* ATAPI events is not supported yet */ 6631 6632 return (AHCI_SUCCESS); 6633 } 6634 /* 6635 * NCQ interrupt handler. Called upon a NCQ command is completed. 6636 * Only be called from ahci_intr_set_device_bits(). 6637 * 6638 * WARNING!!! ahciport_mutex should be acquired before the function is 6639 * called. 6640 */ 6641 static int 6642 ahci_intr_ncq_events(ahci_ctl_t *ahci_ctlp, 6643 ahci_port_t *ahci_portp, ahci_addr_t *addrp) 6644 { 6645 uint32_t port_sactive; 6646 uint32_t port_cmd_issue; 6647 uint32_t issued_tags; 6648 int issued_slot; 6649 uint32_t finished_tags; 6650 int finished_slot; 6651 uint8_t port = addrp->aa_port; 6652 sata_pkt_t *satapkt; 6653 6654 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 6655 "ahci_intr_set_device_bits enter: port %d", port); 6656 6657 mutex_enter(&ahci_portp->ahciport_mutex); 6658 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6659 mutex_exit(&ahci_portp->ahciport_mutex); 6660 return (AHCI_SUCCESS); 6661 } 6662 6663 /* 6664 * First the handler got which commands are finished by checking 6665 * PxSACT register 6666 */ 6667 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6668 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6669 6670 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6671 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 6672 6673 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 6674 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 6675 "port_sactive = 0x%x", port, 6676 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 6677 6678 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 6679 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 6680 6681 /* 6682 * For NCQ commands, the software can determine which command has 6683 * already been transmitted to the device by checking PxCI register. 6684 */ 6685 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6686 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6687 6688 issued_tags = ahci_portp->ahciport_pending_tags & 6689 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 6690 6691 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 6692 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 6693 "port_cmd_issue = 0x%x", port, 6694 ahci_portp->ahciport_pending_tags, port_cmd_issue); 6695 6696 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 6697 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 6698 6699 /* 6700 * Clear ahciport_pending_tags bit when the corresponding command 6701 * is already sent down to the device. 6702 */ 6703 while (issued_tags) { 6704 issued_slot = ddi_ffs(issued_tags) - 1; 6705 if (issued_slot == -1) { 6706 goto next; 6707 } 6708 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 6709 CLEAR_BIT(issued_tags, issued_slot); 6710 } 6711 6712 next: 6713 while (finished_tags) { 6714 finished_slot = ddi_ffs(finished_tags) - 1; 6715 if (finished_slot == -1) { 6716 goto out; 6717 } 6718 6719 /* The command is certainly transmitted to the device */ 6720 ASSERT(!(ahci_portp->ahciport_pending_tags & 6721 (0x1 << finished_slot))); 6722 6723 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 6724 ASSERT(satapkt != NULL); 6725 6726 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 6727 "ahci_intr_set_device_bits: sending up pkt 0x%p " 6728 "with SATA_PKT_COMPLETED", (void *)satapkt); 6729 6730 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 6731 CLEAR_BIT(finished_tags, finished_slot); 6732 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 6733 6734 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6735 } 6736 out: 6737 AHCIDBG(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 6738 "ahci_intr_set_device_bits: port %d " 6739 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 6740 port, ahci_portp->ahciport_pending_ncq_tags, 6741 ahci_portp->ahciport_pending_tags); 6742 6743 mutex_exit(&ahci_portp->ahciport_mutex); 6744 6745 return (AHCI_SUCCESS); 6746 } 6747 6748 /* 6749 * Port multiplier asynchronous notification event handler. Called upon a 6750 * device is hot plugged/pulled. 6751 * 6752 * The async-notification event will only be recorded by ahcipmi_snotif_tags 6753 * here and will be handled by ahci_probe_pmult(). 6754 * 6755 * NOTE: called only from ahci_port_intr(). 6756 */ 6757 static int 6758 ahci_intr_pmult_sntf_events(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6759 uint8_t port) 6760 { 6761 sata_device_t sdevice; 6762 6763 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6764 "ahci_intr_pmult_sntf_events enter: port %d ", port); 6765 6766 /* no hot-plug while attaching process */ 6767 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6768 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 6769 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6770 return (AHCI_SUCCESS); 6771 } 6772 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6773 6774 mutex_enter(&ahci_portp->ahciport_mutex); 6775 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) { 6776 mutex_exit(&ahci_portp->ahciport_mutex); 6777 return (AHCI_SUCCESS); 6778 } 6779 6780 ASSERT(ahci_portp->ahciport_pmult_info != NULL); 6781 6782 ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags = 6783 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6784 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port)); 6785 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6786 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port), 6787 AHCI_SNOTIF_CLEAR_ALL); 6788 6789 if (ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags == 0) { 6790 mutex_exit(&ahci_portp->ahciport_mutex); 6791 return (AHCI_SUCCESS); 6792 } 6793 6794 /* Port Multiplier sub-device hot-plug handler */ 6795 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) { 6796 mutex_exit(&ahci_portp->ahciport_mutex); 6797 return (AHCI_SUCCESS); 6798 } 6799 6800 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_PMULT_SNTF) { 6801 /* Not allowed to re-enter. */ 6802 mutex_exit(&ahci_portp->ahciport_mutex); 6803 return (AHCI_SUCCESS); 6804 } 6805 6806 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_PMULT_SNTF; 6807 6808 /* 6809 * NOTE: 6810 * Even if Asynchronous Notification is supported (and enabled) by 6811 * both controller and the port multiplier, the content of PxSNTF 6812 * register is always set to 0x8000 by async notification event. We 6813 * need to check GSCR[32] on the port multiplier to find out the 6814 * owner of this event. 6815 * This is not accord with SATA spec 2.6 and needs further 6816 * clarification. 6817 */ 6818 /* hot-plug will not reported while reseting. */ 6819 if (ahci_portp->ahciport_reset_in_progress == 1) { 6820 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 6821 "port %d snotif event ignored", port); 6822 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_PMULT_SNTF; 6823 mutex_exit(&ahci_portp->ahciport_mutex); 6824 return (AHCI_SUCCESS); 6825 } 6826 6827 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp, 6828 "PxSNTF is set to 0x%x by port multiplier", 6829 ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags); 6830 6831 /* 6832 * Now we need do some necessary operation and inform SATA framework 6833 * that link/device events has happened. 6834 */ 6835 bzero((void *)&sdevice, sizeof (sata_device_t)); 6836 sdevice.satadev_addr.cport = ahci_ctlp-> 6837 ahcictl_port_to_cport[port]; 6838 sdevice.satadev_addr.pmport = SATA_PMULT_HOSTPORT; 6839 sdevice.satadev_addr.qual = SATA_ADDR_PMULT; 6840 sdevice.satadev_state = SATA_PSTATE_PWRON; 6841 6842 /* Just reject packets, do not stop that port. */ 6843 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 6844 6845 mutex_exit(&ahci_portp->ahciport_mutex); 6846 sata_hba_event_notify( 6847 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6848 &sdevice, 6849 SATA_EVNT_PMULT_LINK_CHANGED); 6850 mutex_enter(&ahci_portp->ahciport_mutex); 6851 6852 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_PMULT_SNTF; 6853 mutex_exit(&ahci_portp->ahciport_mutex); 6854 6855 return (AHCI_SUCCESS); 6856 } 6857 6858 /* 6859 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 6860 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 6861 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 6862 * indicates a COMINIT signal was received. 6863 * 6864 * Hot plug insertion is detected by reception of a COMINIT signal from the 6865 * device. On reception of unsolicited COMINIT, the HBA shall generate a 6866 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 6867 * begin the normal communication negotiation sequence as outlined in the 6868 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 6869 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 6870 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 6871 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 6872 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 6873 * to handle hot plug insertion. In this interrupt handler, just do nothing 6874 * but print some log message and clear the bit. 6875 */ 6876 static int 6877 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 6878 ahci_port_t *ahci_portp, uint8_t port) 6879 { 6880 #if AHCI_DEBUG 6881 uint32_t port_serror; 6882 #endif 6883 6884 mutex_enter(&ahci_portp->ahciport_mutex); 6885 6886 #if AHCI_DEBUG 6887 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6888 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 6889 6890 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 6891 "ahci_intr_port_connect_change: port %d, " 6892 "port_serror = 0x%x", port, port_serror); 6893 #endif 6894 6895 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 6896 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6897 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 6898 SERROR_EXCHANGED_ERR); 6899 6900 mutex_exit(&ahci_portp->ahciport_mutex); 6901 6902 return (AHCI_SUCCESS); 6903 } 6904 6905 /* 6906 * Hot Plug Operation for platforms that support Mechanical Presence 6907 * Switches. 6908 * 6909 * When set, it indicates that a mechanical presence switch attached to this 6910 * port has been opened or closed, which may lead to a change in the connection 6911 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 6912 * are set to '1'. 6913 * 6914 * At the moment, this interrupt is not needed and disabled and we just log 6915 * the debug message. 6916 */ 6917 static int 6918 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 6919 ahci_port_t *ahci_portp, uint8_t port) 6920 { 6921 uint32_t cap_status, port_cmd_status; 6922 6923 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 6924 "ahci_intr_device_mechanical_presence_status enter, " 6925 "port %d", port); 6926 6927 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6928 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 6929 6930 mutex_enter(&ahci_portp->ahciport_mutex); 6931 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6932 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6933 6934 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 6935 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 6936 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6937 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 6938 "the interrupt: cap_status = 0x%x, " 6939 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 6940 mutex_exit(&ahci_portp->ahciport_mutex); 6941 6942 return (AHCI_SUCCESS); 6943 } 6944 6945 #if AHCI_DEBUG 6946 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 6947 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6948 "The mechanical presence switch is open: " 6949 "port %d, port_cmd_status = 0x%x", 6950 port, port_cmd_status); 6951 } else { 6952 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 6953 "The mechanical presence switch is close: " 6954 "port %d, port_cmd_status = 0x%x", 6955 port, port_cmd_status); 6956 } 6957 #endif 6958 6959 mutex_exit(&ahci_portp->ahciport_mutex); 6960 6961 return (AHCI_SUCCESS); 6962 } 6963 6964 /* 6965 * Native Hot Plug Support. 6966 * 6967 * When set, it indicates that the internal PHYRDY signal changed state. 6968 * This bit reflects the state of PxSERR.DIAG.N. 6969 * 6970 * There are three kinds of conditions to generate this interrupt event: 6971 * 1. a device is inserted 6972 * 2. a device is disconnected 6973 * 3. when the link enters/exits a Partial or Slumber interface power 6974 * management state 6975 * 6976 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 6977 * bit may be set due to the link entering the Partial or Slumber power 6978 * management state, rather than due to a hot plug insertion or removal 6979 * event. So far, the interface power management is disabled, so the 6980 * driver can reliably get removal detection notification via the 6981 * PxSERR.DIAG.N bit. 6982 */ 6983 static int 6984 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 6985 ahci_port_t *ahci_portp, uint8_t port) 6986 { 6987 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 6988 sata_device_t sdevice; 6989 int dev_exists_now = 0; 6990 int dev_existed_previously = 0; 6991 ahci_addr_t port_addr; 6992 6993 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 6994 "ahci_intr_phyrdy_change enter, port %d", port); 6995 6996 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 6997 mutex_enter(&ahci_portp->ahciport_mutex); 6998 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6999 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 7000 SERROR_PHY_RDY_CHG); 7001 mutex_exit(&ahci_portp->ahciport_mutex); 7002 7003 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7004 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 7005 (ahci_portp == NULL)) { 7006 /* The whole controller setup is not yet done. */ 7007 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7008 return (AHCI_SUCCESS); 7009 } 7010 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7011 7012 mutex_enter(&ahci_portp->ahciport_mutex); 7013 7014 /* SStatus tells the presence of device. */ 7015 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7016 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 7017 7018 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 7019 dev_exists_now = 1; 7020 } 7021 7022 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 7023 dev_existed_previously = 1; 7024 } 7025 7026 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 7027 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 7028 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 7029 "ahci_intr_phyrdy_change: port %d " 7030 "AHCI_PORT_FLAG_NODEV is cleared", port); 7031 if (dev_exists_now == 0) 7032 dev_existed_previously = 1; 7033 } 7034 7035 bzero((void *)&sdevice, sizeof (sata_device_t)); 7036 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 7037 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 7038 sdevice.satadev_addr.pmport = 0; 7039 sdevice.satadev_state = SATA_PSTATE_PWRON; 7040 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 7041 7042 AHCI_ADDR_SET_PORT(&port_addr, port); 7043 7044 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_HOTPLUG; 7045 if (dev_exists_now) { 7046 if (dev_existed_previously) { /* 1 -> 1 */ 7047 /* Things are fine now. The loss was temporary. */ 7048 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp, 7049 "ahci_intr_phyrdy_change port %d " 7050 "device link lost/established", port); 7051 7052 mutex_exit(&ahci_portp->ahciport_mutex); 7053 sata_hba_event_notify( 7054 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 7055 &sdevice, 7056 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 7057 mutex_enter(&ahci_portp->ahciport_mutex); 7058 7059 } else { /* 0 -> 1 */ 7060 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp, 7061 "ahci_intr_phyrdy_change: port %d " 7062 "device link established", port); 7063 7064 /* 7065 * A new device has been detected. The new device 7066 * might be a port multiplier instead of a drive, so 7067 * we cannot update the signature directly. 7068 */ 7069 (void) ahci_initialize_port(ahci_ctlp, 7070 ahci_portp, &port_addr); 7071 7072 /* Try to start the port */ 7073 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 7074 != AHCI_SUCCESS) { 7075 sdevice.satadev_state |= SATA_PSTATE_FAILED; 7076 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 7077 "ahci_intr_phyrdy_change: port %d failed " 7078 "at start port", port); 7079 } 7080 7081 /* Clear the max queue depth for inserted device */ 7082 ahci_portp->ahciport_max_ncq_tags = 0; 7083 7084 mutex_exit(&ahci_portp->ahciport_mutex); 7085 sata_hba_event_notify( 7086 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 7087 &sdevice, 7088 SATA_EVNT_LINK_ESTABLISHED); 7089 mutex_enter(&ahci_portp->ahciport_mutex); 7090 7091 } 7092 } else { /* No device exists now */ 7093 7094 if (dev_existed_previously) { /* 1 -> 0 */ 7095 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp, 7096 "ahci_intr_phyrdy_change: port %d " 7097 "device link lost", port); 7098 7099 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 7100 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 7101 ahci_portp, port); 7102 7103 if (ahci_portp->ahciport_device_type == 7104 SATA_DTYPE_PMULT) { 7105 ahci_dealloc_pmult(ahci_ctlp, ahci_portp); 7106 } 7107 7108 /* An existing device is lost. */ 7109 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 7110 ahci_portp->ahciport_port_state = SATA_STATE_UNKNOWN; 7111 7112 mutex_exit(&ahci_portp->ahciport_mutex); 7113 sata_hba_event_notify( 7114 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 7115 &sdevice, 7116 SATA_EVNT_LINK_LOST); 7117 mutex_enter(&ahci_portp->ahciport_mutex); 7118 } 7119 } 7120 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_HOTPLUG; 7121 7122 mutex_exit(&ahci_portp->ahciport_mutex); 7123 7124 return (AHCI_SUCCESS); 7125 } 7126 7127 /* 7128 * PxIS.UFS - Unknown FIS Error 7129 * 7130 * This interrupt event means an unknown FIS was received and has been 7131 * copied into system memory. An unknown FIS is not considered an illegal 7132 * FIS, unless the length received is more than 64 bytes. If an unknown 7133 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 7134 * normal operation. If the unknown FIS is more than 64 bytes, then it 7135 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 7136 * a fatal error. 7137 * 7138 * PxIS.IPMS - Incorrect Port Multiplier Status 7139 * 7140 * IPMS Indicates that the HBA received a FIS from a device that did not 7141 * have a command outstanding. The IPMS bit may be set during enumeration 7142 * of devices on a Port Multiplier due to the normal Port Multiplier 7143 * enumeration process. It is recommended that IPMS only be used after 7144 * enumeration is complete on the Port Multiplier (copied from spec). 7145 * 7146 * PxIS.OFS - Overflow Error 7147 * 7148 * Command list overflow is defined as software building a command table 7149 * that has fewer total bytes than the transaction given to the device. 7150 * On device writes, the HBA will run out of data, and on reads, there 7151 * will be no room to put the data. 7152 * 7153 * For an overflow on data read, either PIO or DMA, the HBA will set 7154 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 7155 * non-fatal error when the HBA can continues. Sometimes, it will cause 7156 * a fatal error and need the software to do something. 7157 * 7158 * For an overflow on data write, setting PxIS.OFS is optional for both 7159 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 7160 * software to clean up from this serious error. 7161 * 7162 * PxIS.INFS - Interface Non-Fatal Error 7163 * 7164 * This interrupt event indicates that the HBA encountered an error on 7165 * the Serial ATA interface but was able to continue operation. The kind 7166 * of error usually occurred during a non-Data FIS, and under this condition 7167 * the FIS will be re-transmitted by HBA automatically. 7168 * 7169 * When the FMA is implemented, there should be a stat structure to 7170 * record how many every kind of error happens. 7171 */ 7172 static int 7173 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 7174 uint8_t port, uint32_t intr_status) 7175 { 7176 uint32_t port_serror; 7177 #if AHCI_DEBUG 7178 uint32_t port_cmd_status; 7179 uint32_t port_cmd_issue; 7180 uint32_t port_sactive; 7181 int current_slot; 7182 uint32_t current_tags; 7183 sata_pkt_t *satapkt; 7184 ahci_cmd_header_t *cmd_header; 7185 uint32_t cmd_dmacount; 7186 #endif 7187 7188 mutex_enter(&ahci_portp->ahciport_mutex); 7189 7190 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7191 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 7192 7193 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 7194 "ahci_intr_non_fatal_error: port %d, " 7195 "PxSERR = 0x%x, PxIS = 0x%x ", port, port_serror, intr_status); 7196 7197 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 7198 7199 if (intr_status & AHCI_INTR_STATUS_UFS) { 7200 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, 7201 "ahci port %d has unknown FIS error", port); 7202 7203 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 7204 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7205 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 7206 SERROR_FIS_TYPE); 7207 } 7208 7209 #if AHCI_DEBUG 7210 if (intr_status & AHCI_INTR_STATUS_IPMS) { 7211 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci port %d " 7212 "has Incorrect Port Multiplier Status error", port); 7213 } 7214 7215 if (intr_status & AHCI_INTR_STATUS_OFS) { 7216 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7217 "ahci port %d has overflow error", port); 7218 } 7219 7220 if (intr_status & AHCI_INTR_STATUS_INFS) { 7221 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7222 "ahci port %d has interface non fatal error", port); 7223 } 7224 7225 /* 7226 * Record the error occurred command's slot. 7227 */ 7228 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 7229 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7230 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7231 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7232 7233 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 7234 AHCI_CMD_STATUS_CCS_SHIFT; 7235 7236 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7237 satapkt = ahci_portp->ahciport_err_retri_pkt; 7238 ASSERT(satapkt != NULL); 7239 ASSERT(current_slot == 0); 7240 } else { 7241 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 7242 } 7243 7244 if (satapkt != NULL) { 7245 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7246 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 7247 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 7248 satapkt->satapkt_cmd.satacmd_cmd_reg); 7249 7250 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7251 "ahci_intr_non_fatal_error: port %d, " 7252 "satapkt 0x%p is being processed when error occurs", 7253 port, (void *)satapkt); 7254 7255 /* 7256 * PRD Byte Count field of command header is not 7257 * required to reflect the total number of bytes 7258 * transferred when an overflow occurs, so here 7259 * just log the value. 7260 */ 7261 cmd_dmacount = 7262 ahci_portp->ahciport_prd_bytecounts[current_slot]; 7263 if (cmd_dmacount) { 7264 cmd_header = &ahci_portp-> 7265 ahciport_cmd_list[current_slot]; 7266 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7267 "ahci_intr_non_fatal_error: port %d, " 7268 "PRD Byte Count = 0x%x, " 7269 "ahciport_prd_bytecounts = 0x%x", port, 7270 cmd_header->ahcich_prd_byte_count, 7271 cmd_dmacount); 7272 } 7273 } 7274 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7275 /* 7276 * For queued command, list those command which have already 7277 * been transmitted to the device and still not completed. 7278 */ 7279 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7280 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 7281 7282 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7283 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 7284 7285 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 7286 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 7287 "port_sactive = 0x%x port_cmd_issue = 0x%x", 7288 ahci_portp->ahciport_pending_ncq_tags, 7289 port_sactive, port_cmd_issue); 7290 7291 current_tags = ahci_portp->ahciport_pending_ncq_tags & 7292 port_sactive & ~port_cmd_issue & 7293 AHCI_NCQ_SLOT_MASK(ahci_portp); 7294 7295 while (current_tags) { 7296 current_slot = ddi_ffs(current_tags) - 1; 7297 if (current_slot == -1) { 7298 goto out; 7299 } 7300 7301 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 7302 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 7303 ahci_ctlp, "ahci_intr_non_fatal_error: " 7304 "port %d, satapkt 0x%p is outstanding when " 7305 "error occurs", port, (void *)satapkt); 7306 7307 CLEAR_BIT(current_tags, current_slot); 7308 } 7309 } 7310 out: 7311 #endif 7312 mutex_exit(&ahci_portp->ahciport_mutex); 7313 7314 return (AHCI_SUCCESS); 7315 } 7316 7317 /* 7318 * According to the AHCI spec, the error types include system memory 7319 * errors, interface errors, port multiplier errors, device errors, 7320 * command list overflow, command list underflow, native command 7321 * queuing tag errors and pio data transfer errors. 7322 * 7323 * System memory errors such as target abort, master abort, and parity 7324 * may cause the host to stop, and they are serious errors and needed 7325 * to be recovered with software intervention. When system software 7326 * has given a pointer to the HBA that doesn't exist in physical memory, 7327 * a master/target abort error occurs, and PxIS.HBFS will be set. A 7328 * data error such as CRC or parity occurs, the HBA aborts the transfer 7329 * (if necessary) and PxIS.HBDS will be set. 7330 * 7331 * Interface errors are errors that occur due to electrical issues on 7332 * the interface, or protocol miscommunication between the device and 7333 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 7334 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 7335 * causes PxIS.IFS/PxIS.INFS to be set are 7336 * 1. in PxSERR.ERR, P bit is set to '1' 7337 * 2. in PxSERR.DIAG, C or H bit is set to '1' 7338 * 3. PhyRdy drop unexpectly, N bit is set to '1' 7339 * If the error occurred during a non-data FIS, the FIS must be 7340 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 7341 * the error occurred during a data FIS, the transfer will stop, so 7342 * the error is fatal and PxIS.IFS is set. 7343 * 7344 * When a FIS arrives that updates the taskfile, the HBA checks to see 7345 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 7346 * stops processing any more commands. 7347 * 7348 * Command list overflow is defined as software building a command table 7349 * that has fewer total bytes than the transaction given to the device. 7350 * On device writes, the HBA will run out of data, and on reads, there 7351 * will be no room to put the data. For an overflow on data read, either 7352 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 7353 * For an overflow on data write, setting PxIS.OFS is optional for both 7354 * DMA and PIO, and a COMRESET is required by software to clean up from 7355 * this serious error. 7356 * 7357 * Command list underflow is defined as software building a command 7358 * table that has more total bytes than the transaction given to the 7359 * device. For data writes, both PIO and DMA, the device will detect 7360 * an error and end the transfer. And these errors are most likely going 7361 * to be fatal errors that will cause the port to be restarted. For 7362 * data reads, the HBA updates its PRD byte count, and may be 7363 * able to continue normally, but is not required to. And The HBA is 7364 * not required to detect underflow conditions for native command 7365 * queuing command. 7366 * 7367 * The HBA does not actively check incoming DMA Setup FISes to ensure 7368 * that the PxSACT register bit for that slot is set. Existing error 7369 * mechanisms, such as host bus failure, or bad protocol, are used to 7370 * recover from this case. 7371 * 7372 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 7373 * DATA FIS must be an integral number of Dwords. If the HBA receives 7374 * a request which is not an integral number of Dwords, the HBA 7375 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 7376 * software restarts the port. And the HBA ensures that the size 7377 * of the DATA FIS received during a PIO command matches the size in 7378 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 7379 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 7380 * stop running until software restarts the port. 7381 */ 7382 /* 7383 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 7384 * 7385 * PxIS.IFS indicates that the hba encountered an error on the serial ata 7386 * interface which caused the transfer to stop. 7387 * 7388 * PxIS.HBDS indicates that the hba encountered a data error 7389 * (uncorrectable ecc/parity) when reading from or writing to system memory. 7390 * 7391 * PxIS.HBFS indicates that the hba encountered a host bus error that it 7392 * cannot recover from, such as a bad software pointer. 7393 * 7394 * PxIS.TFES is set whenever the status register is updated by the device 7395 * and the error bit (bit 0) is set. 7396 */ 7397 static int 7398 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 7399 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 7400 { 7401 uint32_t port_cmd_status; 7402 uint32_t port_serror; 7403 uint32_t task_file_status; 7404 int failed_slot; 7405 sata_pkt_t *spkt = NULL; 7406 uint8_t err_byte; 7407 ahci_event_arg_t *args; 7408 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7409 7410 mutex_enter(&ahci_portp->ahciport_mutex); 7411 7412 /* 7413 * ahci_intr_phyrdy_change() may have rendered it to 7414 * SATA_DTYPE_NONE. 7415 */ 7416 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 7417 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 7418 "ahci_intr_fatal_error: port %d no device attached, " 7419 "and just return without doing anything", port); 7420 goto out0; 7421 } 7422 7423 if (intr_status & AHCI_INTR_STATUS_TFES) { 7424 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7425 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 7426 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7427 "ahci_intr_fatal_error: port %d " 7428 "task_file_status = 0x%x", port, task_file_status); 7429 } 7430 7431 /* 7432 * Here we just log the fatal error info in interrupt context. 7433 * Misc recovery processing will be handled in task queue. 7434 */ 7435 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7436 /* 7437 * Read PxCMD.CCS to determine the slot that the HBA 7438 * was processing when the error occurred. 7439 */ 7440 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7441 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7442 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 7443 AHCI_CMD_STATUS_CCS_SHIFT; 7444 7445 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 7446 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7447 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 7448 "fatal error occurred for port %d", spkt, port); 7449 7450 /* A Task File Data error. */ 7451 if (intr_status & AHCI_INTR_STATUS_TFES) { 7452 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 7453 >> AHCI_TFD_ERR_SHIFT; 7454 7455 /* 7456 * Won't emit the error message if it is an IDENTIFY 7457 * DEVICE command sent to an ATAPI device. 7458 */ 7459 if ((spkt != NULL) && 7460 (spkt->satapkt_cmd.satacmd_cmd_reg == 7461 SATAC_ID_DEVICE) && 7462 (err_byte == SATA_ERROR_ABORT)) 7463 goto out1; 7464 7465 /* 7466 * Won't emit the error message if it is an ATAPI PACKET 7467 * command 7468 */ 7469 if ((spkt != NULL) && 7470 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 7471 goto out1; 7472 } 7473 } 7474 7475 /* print the fatal error type */ 7476 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 7477 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7478 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 7479 7480 /* print PxSERR related error message */ 7481 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 7482 7483 /* print task file register value */ 7484 if (intr_status & AHCI_INTR_STATUS_TFES) { 7485 cmn_err(CE_WARN, "!ahci%d: ahci port %d task_file_status " 7486 "= 0x%x", instance, port, task_file_status); 7487 } 7488 7489 out1: 7490 /* Prepare the argument for the taskq */ 7491 args = ahci_portp->ahciport_event_args; 7492 args->ahciea_ctlp = (void *)ahci_ctlp; 7493 args->ahciea_portp = (void *)ahci_portp; 7494 args->ahciea_event = intr_status; 7495 AHCI_ADDR_SET_PORT((ahci_addr_t *)args->ahciea_addrp, port); 7496 7497 /* Start the taskq to handle error recovery */ 7498 if ((ddi_taskq_dispatch(ahci_portp->ahciport_event_taskq, 7499 ahci_events_handler, 7500 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 7501 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 7502 "failed", instance); 7503 } 7504 out0: 7505 mutex_exit(&ahci_portp->ahciport_mutex); 7506 7507 return (AHCI_SUCCESS); 7508 } 7509 7510 /* 7511 * Hot Plug Operation for platforms that support Cold Presence Detect. 7512 * 7513 * When set, a device status has changed as detected by the cold presence 7514 * detect logic. This bit can either be set due to a non-connected port 7515 * receiving a device, or a connected port having its device removed. 7516 * This bit is only valid if the port supports cold presence detect as 7517 * indicated by PxCMD.CPD set to '1'. 7518 * 7519 * At the moment, this interrupt is not needed and disabled and we just 7520 * log the debug message. 7521 */ 7522 static int 7523 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 7524 ahci_port_t *ahci_portp, uint8_t port) 7525 { 7526 uint32_t port_cmd_status; 7527 sata_device_t sdevice; 7528 7529 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 7530 "ahci_intr_cold_port_detect enter, port %d", port); 7531 7532 mutex_enter(&ahci_portp->ahciport_mutex); 7533 7534 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7535 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7536 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 7537 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 7538 "port %d does not support cold presence detect, so " 7539 "we just ignore this interrupt", port); 7540 mutex_exit(&ahci_portp->ahciport_mutex); 7541 return (AHCI_SUCCESS); 7542 } 7543 7544 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 7545 "port %d device status has changed", port); 7546 7547 bzero((void *)&sdevice, sizeof (sata_device_t)); 7548 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 7549 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 7550 sdevice.satadev_addr.pmport = 0; 7551 sdevice.satadev_state = SATA_PSTATE_PWRON; 7552 7553 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 7554 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 7555 "port %d: a device is hot plugged", port); 7556 mutex_exit(&ahci_portp->ahciport_mutex); 7557 sata_hba_event_notify( 7558 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 7559 &sdevice, 7560 SATA_EVNT_DEVICE_ATTACHED); 7561 mutex_enter(&ahci_portp->ahciport_mutex); 7562 7563 } else { 7564 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 7565 "port %d: a device is hot unplugged", port); 7566 mutex_exit(&ahci_portp->ahciport_mutex); 7567 sata_hba_event_notify( 7568 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 7569 &sdevice, 7570 SATA_EVNT_DEVICE_DETACHED); 7571 mutex_enter(&ahci_portp->ahciport_mutex); 7572 } 7573 7574 mutex_exit(&ahci_portp->ahciport_mutex); 7575 7576 return (AHCI_SUCCESS); 7577 } 7578 7579 /* 7580 * Enable the interrupts for a particular port. 7581 * 7582 * WARNING!!! ahciport_mutex should be acquired before the function 7583 * is called. 7584 */ 7585 static void 7586 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 7587 { 7588 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 7589 "ahci_enable_port_intrs enter, port %d", port); 7590 7591 /* 7592 * Clear port interrupt status before enabling interrupt 7593 */ 7594 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7595 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 7596 AHCI_PORT_INTR_MASK); 7597 7598 /* 7599 * Clear the pending bit from IS.IPS 7600 */ 7601 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7602 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 7603 7604 /* 7605 * Enable the following interrupts: 7606 * Device to Host Register FIS Interrupt (DHRS) 7607 * PIO Setup FIS Interrupt (PSS) 7608 * Set Device Bits Interrupt (SDBS) 7609 * Unknown FIS Interrupt (UFS) 7610 * Port Connect Change Status (PCS) 7611 * PhyRdy Change Status (PRCS) 7612 * Overflow Status (OFS) 7613 * Interface Non-fatal Error Status (INFS) 7614 * Interface Fatal Error Status (IFS) 7615 * Host Bus Data Error Status (HBDS) 7616 * Host Bus Fatal Error Status (HBFS) 7617 * Task File Error Status (TFES) 7618 */ 7619 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7620 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 7621 (AHCI_INTR_STATUS_DHRS | 7622 AHCI_INTR_STATUS_PSS | 7623 AHCI_INTR_STATUS_SDBS | 7624 AHCI_INTR_STATUS_UFS | 7625 AHCI_INTR_STATUS_DPS | 7626 AHCI_INTR_STATUS_PCS | 7627 AHCI_INTR_STATUS_PRCS | 7628 AHCI_INTR_STATUS_OFS | 7629 AHCI_INTR_STATUS_INFS | 7630 AHCI_INTR_STATUS_IFS | 7631 AHCI_INTR_STATUS_HBDS | 7632 AHCI_INTR_STATUS_HBFS | 7633 AHCI_INTR_STATUS_TFES)); 7634 } 7635 7636 /* 7637 * Enable interrupts for all the ports. 7638 * 7639 * WARNING!!! ahcictl_mutex should be acquired before the function 7640 * is called. 7641 */ 7642 static void 7643 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 7644 { 7645 uint32_t ghc_control; 7646 7647 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter", NULL); 7648 7649 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7650 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 7651 7652 ghc_control |= AHCI_HBA_GHC_IE; 7653 7654 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7655 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 7656 } 7657 7658 /* 7659 * Disable interrupts for a particular port. 7660 * 7661 * WARNING!!! ahciport_mutex should be acquired before the function 7662 * is called. 7663 */ 7664 static void 7665 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 7666 { 7667 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 7668 "ahci_disable_port_intrs enter, port %d", port); 7669 7670 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7671 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 7672 } 7673 7674 /* 7675 * Disable interrupts for the whole HBA. 7676 * 7677 * The global bit is cleared, then all interrupt sources from all 7678 * ports are disabled. 7679 * 7680 * WARNING!!! ahcictl_mutex should be acquired before the function 7681 * is called. 7682 */ 7683 static void 7684 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 7685 { 7686 uint32_t ghc_control; 7687 7688 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter", 7689 NULL); 7690 7691 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7692 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 7693 7694 ghc_control &= ~ AHCI_HBA_GHC_IE; 7695 7696 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7697 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 7698 } 7699 7700 /* 7701 * Handle FIXED or MSI interrupts. 7702 */ 7703 /* 7704 * According to AHCI spec, the HBA may support several interrupt modes: 7705 * * pin based interrupts (FIXED) 7706 * * single MSI message interrupts 7707 * * multiple MSI based message interrupts 7708 * 7709 * For pin based interrupts, the software interrupt handler need to check IS 7710 * register to find out which port has pending interrupts. And then check 7711 * PxIS register to find out which interrupt events happened on that port. 7712 * 7713 * For single MSI message interrupts, MSICAP.MC.MSIE is set with '1', and 7714 * MSICAP.MC.MME is set with '0'. This mode is similar to pin based interrupts 7715 * in that software interrupt handler need to check IS register to determine 7716 * which port triggered the interrupts since it uses a single message for all 7717 * port interrupts. 7718 * 7719 * HBA may optionally support multiple MSI message for better performance. In 7720 * this mode, each port may have its own interrupt message, and thus generation 7721 * of interrupts is no longer controlled through the IS register. MSICAP.MC.MMC 7722 * represents a power-of-2 wrapper on the number of implemented ports, and 7723 * the mapping of ports to interrupts is done in a 1-1 relationship, up to the 7724 * maximum number of assigned interrupts. When the number of MSI messages 7725 * allocated is less than the number requested, then hardware may have two 7726 * implementation behaviors: 7727 * * assign each ports its own interrupt and then force all additional 7728 * ports to share the last interrupt message, and this condition is 7729 * indicated by clearing GHC.MRSM to '0' 7730 * * revert to single MSI mode, indicated by setting GHC.MRSM to '1' 7731 * When multiple-message MSI is enabled, hardware will still set IS register 7732 * as single message case. And this IS register may be used by software when 7733 * fewer than the requested number of messages is granted in order to determine 7734 * which port had the interrupt. 7735 * 7736 * Note: The current ahci driver only supports the first two interrupt modes: 7737 * pin based interrupts and single MSI message interrupts, and the reason 7738 * is indicated in below code. 7739 */ 7740 static int 7741 ahci_add_intrs(ahci_ctl_t *ahci_ctlp, int intr_type) 7742 { 7743 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 7744 int count, avail, actual; 7745 int i, rc; 7746 7747 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 7748 "ahci_add_intrs enter interrupt type 0x%x", intr_type); 7749 7750 /* get number of interrupts. */ 7751 rc = ddi_intr_get_nintrs(dip, intr_type, &count); 7752 if ((rc != DDI_SUCCESS) || (count == 0)) { 7753 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7754 "ddi_intr_get_nintrs() failed, " 7755 "rc %d count %d\n", rc, count); 7756 return (DDI_FAILURE); 7757 } 7758 7759 /* get number of available interrupts. */ 7760 rc = ddi_intr_get_navail(dip, intr_type, &avail); 7761 if ((rc != DDI_SUCCESS) || (avail == 0)) { 7762 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7763 "ddi_intr_get_navail() failed, " 7764 "rc %d avail %d\n", rc, avail); 7765 return (DDI_FAILURE); 7766 } 7767 7768 #if AHCI_DEBUG 7769 if (avail < count) { 7770 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7771 "ddi_intr_get_nintrs returned %d, navail() returned %d", 7772 count, avail); 7773 } 7774 #endif 7775 7776 /* 7777 * Note: So far Solaris restricts the maximum number of messages for 7778 * x86 to 2, that is avail is 2, so here we set the count with 1 to 7779 * force the driver to use single MSI message interrupt. In future if 7780 * Solaris remove the restriction, then we need to delete the below 7781 * code and try to use multiple interrupt routine to gain better 7782 * performance. 7783 */ 7784 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 7785 AHCIDBG(AHCIDBG_INTR, ahci_ctlp, 7786 "force to use one interrupt routine though the " 7787 "HBA supports %d interrupt", count); 7788 count = 1; 7789 } 7790 7791 /* Allocate an array of interrupt handles. */ 7792 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 7793 ahci_ctlp->ahcictl_intr_htable = 7794 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 7795 7796 /* call ddi_intr_alloc(). */ 7797 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 7798 intr_type, 0, count, &actual, DDI_INTR_ALLOC_NORMAL); 7799 7800 if ((rc != DDI_SUCCESS) || (actual == 0)) { 7801 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7802 "ddi_intr_alloc() failed, rc %d count %d actual %d " 7803 "avail %d\n", rc, count, actual, avail); 7804 kmem_free(ahci_ctlp->ahcictl_intr_htable, 7805 ahci_ctlp->ahcictl_intr_size); 7806 return (DDI_FAILURE); 7807 } 7808 7809 /* use interrupt count returned */ 7810 #if AHCI_DEBUG 7811 if (actual < count) { 7812 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7813 "Requested: %d, Received: %d", count, actual); 7814 } 7815 #endif 7816 7817 ahci_ctlp->ahcictl_intr_cnt = actual; 7818 7819 /* 7820 * Get priority for first, assume remaining are all the same. 7821 */ 7822 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 7823 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 7824 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7825 "ddi_intr_get_pri() failed", NULL); 7826 7827 /* Free already allocated intr. */ 7828 for (i = 0; i < actual; i++) { 7829 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]); 7830 } 7831 7832 kmem_free(ahci_ctlp->ahcictl_intr_htable, 7833 ahci_ctlp->ahcictl_intr_size); 7834 return (DDI_FAILURE); 7835 } 7836 7837 /* Test for high level interrupt. */ 7838 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 7839 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7840 "ahci_add_intrs: Hi level intr not supported", NULL); 7841 7842 /* Free already allocated intr. */ 7843 for (i = 0; i < actual; i++) { 7844 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]); 7845 } 7846 7847 kmem_free(ahci_ctlp->ahcictl_intr_htable, 7848 sizeof (ddi_intr_handle_t)); 7849 7850 return (DDI_FAILURE); 7851 } 7852 7853 /* Call ddi_intr_add_handler(). */ 7854 for (i = 0; i < actual; i++) { 7855 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[i], 7856 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 7857 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7858 "ddi_intr_add_handler() failed", NULL); 7859 7860 /* Free already allocated intr. */ 7861 for (i = 0; i < actual; i++) { 7862 (void) ddi_intr_free( 7863 ahci_ctlp->ahcictl_intr_htable[i]); 7864 } 7865 7866 kmem_free(ahci_ctlp->ahcictl_intr_htable, 7867 ahci_ctlp->ahcictl_intr_size); 7868 return (DDI_FAILURE); 7869 } 7870 } 7871 7872 if (ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 7873 &ahci_ctlp->ahcictl_intr_cap) != DDI_SUCCESS) { 7874 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 7875 "ddi_intr_get_cap() failed", NULL); 7876 7877 /* Free already allocated intr. */ 7878 for (i = 0; i < actual; i++) { 7879 (void) ddi_intr_free( 7880 ahci_ctlp->ahcictl_intr_htable[i]); 7881 } 7882 7883 kmem_free(ahci_ctlp->ahcictl_intr_htable, 7884 ahci_ctlp->ahcictl_intr_size); 7885 return (DDI_FAILURE); 7886 } 7887 7888 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 7889 /* Call ddi_intr_block_enable() for MSI. */ 7890 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 7891 ahci_ctlp->ahcictl_intr_cnt); 7892 } else { 7893 /* Call ddi_intr_enable() for FIXED or MSI non block enable. */ 7894 for (i = 0; i < ahci_ctlp->ahcictl_intr_cnt; i++) { 7895 (void) ddi_intr_enable( 7896 ahci_ctlp->ahcictl_intr_htable[i]); 7897 } 7898 } 7899 7900 return (DDI_SUCCESS); 7901 } 7902 7903 /* 7904 * Removes the registered interrupts irrespective of whether they 7905 * were legacy or MSI. 7906 * 7907 * WARNING!!! The controller interrupts must be disabled before calling 7908 * this routine. 7909 */ 7910 static void 7911 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 7912 { 7913 int x; 7914 7915 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered", NULL); 7916 7917 /* Disable all interrupts. */ 7918 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 7919 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 7920 /* Call ddi_intr_block_disable(). */ 7921 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 7922 ahci_ctlp->ahcictl_intr_cnt); 7923 } else { 7924 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 7925 (void) ddi_intr_disable( 7926 ahci_ctlp->ahcictl_intr_htable[x]); 7927 } 7928 } 7929 7930 /* Call ddi_intr_remove_handler(). */ 7931 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 7932 (void) ddi_intr_remove_handler( 7933 ahci_ctlp->ahcictl_intr_htable[x]); 7934 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 7935 } 7936 7937 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 7938 } 7939 7940 /* 7941 * This routine tries to put port into P:NotRunning state by clearing 7942 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 7943 * and PxCMD.CR to '0'. 7944 * 7945 * WARNING!!! ahciport_mutex should be acquired before the function 7946 * is called. 7947 */ 7948 static int 7949 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 7950 ahci_port_t *ahci_portp, uint8_t port) 7951 { 7952 uint32_t port_cmd_status; 7953 int loop_count; 7954 7955 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, 7956 "ahci_put_port_into_notrunning_state enter: port %d", port); 7957 7958 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7959 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7960 7961 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 7962 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 7963 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 7964 7965 /* Wait until PxCMD.CR is cleared */ 7966 loop_count = 0; 7967 do { 7968 port_cmd_status = 7969 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7970 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7971 7972 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 7973 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, 7974 "clearing port %d CMD.CR timeout, " 7975 "port_cmd_status = 0x%x", port, 7976 port_cmd_status); 7977 /* 7978 * We are effectively timing out after 0.5 sec. 7979 * This value is specified in AHCI spec. 7980 */ 7981 break; 7982 } 7983 7984 /* Wait for 10 millisec */ 7985 drv_usecwait(AHCI_10MS_USECS); 7986 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 7987 7988 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 7989 7990 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 7991 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 7992 "ahci_put_port_into_notrunning_state: failed to clear " 7993 "PxCMD.CR to '0' after loop count: %d, and " 7994 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 7995 return (AHCI_FAILURE); 7996 } else { 7997 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 7998 "ahci_put_port_into_notrunning_state: succeeded to clear " 7999 "PxCMD.CR to '0' after loop count: %d, and " 8000 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 8001 return (AHCI_SUCCESS); 8002 } 8003 } 8004 8005 /* 8006 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 8007 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 8008 * stable state, then set PxCMD.ST to '1' to start the port directly. 8009 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 8010 * COMRESET to the device to put it in an idle state. 8011 * 8012 * The fifth argument returns whether the port reset is involved during 8013 * the process. 8014 * 8015 * The routine will be called under following scenarios: 8016 * + To reset the HBA 8017 * + To abort the packet(s) 8018 * + To reset the port 8019 * + To activate the port 8020 * + Fatal error recovery 8021 * + To abort the timeout packet(s) 8022 * 8023 * WARNING!!! ahciport_mutex should be acquired before the function 8024 * is called. And ahciport_mutex will be released before the reset 8025 * event is reported to sata module by calling sata_hba_event_notify, 8026 * and then be acquired again later. 8027 * 8028 * NOTES!!! During this procedure, PxSERR register will be cleared, and 8029 * according to the spec, the clearance of three bits will also clear 8030 * three interrupt status bits. 8031 * 1. PxSERR.DIAG.F will clear PxIS.UFS 8032 * 2. PxSERR.DIAG.X will clear PxIS.PCS 8033 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 8034 * 8035 * Among these three interrupt events, the driver needs to take care of 8036 * PxIS.PRCS, which is the hot plug event. When the driver found out 8037 * a device was unplugged, it will call the interrupt handler. 8038 */ 8039 static int 8040 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 8041 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 8042 { 8043 uint32_t port_sstatus; 8044 uint32_t task_file_status; 8045 sata_device_t sdevice; 8046 int rval; 8047 ahci_addr_t addr_port; 8048 ahci_pmult_info_t *