1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 #include <sys/param.h> 30 #include <sys/types.h> 31 #include <sys/vmparam.h> 32 #include <sys/systm.h> 33 #include <sys/signal.h> 34 #include <sys/stack.h> 35 #include <sys/regset.h> 36 #include <sys/privregs.h> 37 #include <sys/frame.h> 38 #include <sys/proc.h> 39 #include <sys/psw.h> 40 #include <sys/siginfo.h> 41 #include <sys/cpuvar.h> 42 #include <sys/asm_linkage.h> 43 #include <sys/kmem.h> 44 #include <sys/errno.h> 45 #include <sys/bootconf.h> 46 #include <sys/archsystm.h> 47 #include <sys/debug.h> 48 #include <sys/elf.h> 49 #include <sys/spl.h> 50 #include <sys/time.h> 51 #include <sys/atomic.h> 52 #include <sys/sysmacros.h> 53 #include <sys/cmn_err.h> 54 #include <sys/modctl.h> 55 #include <sys/kobj.h> 56 #include <sys/panic.h> 57 #include <sys/reboot.h> 58 #include <sys/time.h> 59 #include <sys/fp.h> 60 #include <sys/x86_archext.h> 61 #include <sys/auxv.h> 62 #include <sys/auxv_386.h> 63 #include <sys/dtrace.h> 64 #include <sys/brand.h> 65 #include <sys/machbrand.h> 66 67 extern const struct fnsave_state x87_initial; 68 extern const struct fxsave_state sse_initial; 69 70 /* 71 * Map an fnsave-formatted save area into an fxsave-formatted save area. 72 * 73 * Most fields are the same width, content and semantics. However 74 * the tag word is compressed. 75 */ 76 static void 77 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx) 78 { 79 uint_t i, tagbits; 80 81 fx->fx_fcw = fn->f_fcw; 82 fx->fx_fsw = fn->f_fsw; 83 84 /* 85 * copy element by element (because of holes) 86 */ 87 for (i = 0; i < 8; i++) 88 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0], 89 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */ 90 91 /* 92 * synthesize compressed tag bits 93 */ 94 fx->fx_fctw = 0; 95 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2) 96 if ((tagbits & 3) != 3) 97 fx->fx_fctw |= (1 << i); 98 99 fx->fx_fop = fn->f_fop; 100 101 #if defined(__amd64) 102 fx->fx_rip = (uint64_t)fn->f_eip; 103 fx->fx_rdp = (uint64_t)fn->f_dp; 104 #else 105 fx->fx_eip = fn->f_eip; 106 fx->fx_cs = fn->f_cs; 107 fx->__fx_ign0 = 0; 108 fx->fx_dp = fn->f_dp; 109 fx->fx_ds = fn->f_ds; 110 fx->__fx_ign1 = 0; 111 #endif 112 } 113 114 /* 115 * Map from an fxsave-format save area to an fnsave-format save area. 116 */ 117 static void 118 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn) 119 { 120 uint_t i, top, tagbits; 121 122 fn->f_fcw = fx->fx_fcw; 123 fn->__f_ign0 = 0; 124 fn->f_fsw = fx->fx_fsw; 125 fn->__f_ign1 = 0; 126 127 top = (fx->fx_fsw & FPS_TOP) >> 11; 128 129 /* 130 * copy element by element (because of holes) 131 */ 132 for (i = 0; i < 8; i++) 133 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0], 134 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */ 135 136 /* 137 * synthesize uncompressed tag bits 138 */ 139 fn->f_ftw = 0; 140 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) { 141 uint_t ibit, expo; 142 const uint16_t *fpp; 143 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 }; 144 145 if ((tagbits & 1) == 0) { 146 fn->f_ftw |= 3 << (i << 1); /* empty */ 147 continue; 148 } 149 150 /* 151 * (tags refer to *physical* registers) 152 */ 153 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0]; 154 ibit = fpp[3] >> 15; 155 expo = fpp[4] & 0x7fff; 156 157 if (ibit && expo != 0 && expo != 0x7fff) 158 continue; /* valid fp number */ 159 160 if (bcmp(fpp, &zero, sizeof (zero))) 161 fn->f_ftw |= 2 << (i << 1); /* NaN */ 162 else 163 fn->f_ftw |= 1 << (i << 1); /* fp zero */ 164 } 165 166 fn->f_fop = fx->fx_fop; 167 168 fn->__f_ign2 = 0; 169 #if defined(__amd64) 170 fn->f_eip = (uint32_t)fx->fx_rip; 171 fn->f_cs = U32CS_SEL; 172 fn->f_dp = (uint32_t)fx->fx_rdp; 173 fn->f_ds = UDS_SEL; 174 #else 175 fn->f_eip = fx->fx_eip; 176 fn->f_cs = fx->fx_cs; 177 fn->f_dp = fx->fx_dp; 178 fn->f_ds = fx->fx_ds; 179 #endif 180 fn->__f_ign3 = 0; 181 } 182 183 /* 184 * Map from an fpregset_t into an fxsave-format save area 185 */ 186 static void 187 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx) 188 { 189 #if defined(__amd64) 190 bcopy(fp, fx, sizeof (*fx)); 191 #else 192 const struct fpchip_state *fc = &fp->fp_reg_set.fpchip_state; 193 194 fnsave_to_fxsave((const struct fnsave_state *)fc, fx); 195 fx->fx_mxcsr = fc->mxcsr; 196 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm)); 197 #endif 198 /* 199 * avoid useless #gp exceptions - mask reserved bits 200 */ 201 fx->fx_mxcsr &= sse_mxcsr_mask; 202 } 203 204 /* 205 * Map from an fxsave-format save area into a fpregset_t 206 */ 207 static void 208 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp) 209 { 210 #if defined(__amd64) 211 bcopy(fx, fp, sizeof (*fx)); 212 #else 213 struct fpchip_state *fc = &fp->fp_reg_set.fpchip_state; 214 215 fxsave_to_fnsave(fx, (struct fnsave_state *)fc); 216 fc->mxcsr = fx->fx_mxcsr; 217 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm)); 218 #endif 219 } 220 221 #if defined(_SYSCALL32_IMPL) 222 static void 223 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx) 224 { 225 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state; 226 227 fnsave_to_fxsave((const struct fnsave_state *)fc, fx); 228 /* 229 * avoid useless #gp exceptions - mask reserved bits 230 */ 231 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr; 232 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm)); 233 } 234 235 static void 236 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp) 237 { 238 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state; 239 240 fxsave_to_fnsave(fx, (struct fnsave_state *)fc); 241 fc->mxcsr = fx->fx_mxcsr; 242 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm)); 243 } 244 245 static void 246 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst) 247 { 248 fxsave_to_fpregset32((struct fxsave_state *)src, dst); 249 dst->fp_reg_set.fpchip_state.status = 250 src->fp_reg_set.fpchip_state.status; 251 dst->fp_reg_set.fpchip_state.xstatus = 252 src->fp_reg_set.fpchip_state.xstatus; 253 } 254 255 static void 256 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst) 257 { 258 fpregset32_to_fxsave(src, (struct fxsave_state *)dst); 259 dst->fp_reg_set.fpchip_state.status = 260 src->fp_reg_set.fpchip_state.status; 261 dst->fp_reg_set.fpchip_state.xstatus = 262 src->fp_reg_set.fpchip_state.xstatus; 263 } 264 #endif 265 266 /* 267 * Set floating-point registers from a native fpregset_t. 268 */ 269 void 270 setfpregs(klwp_t *lwp, fpregset_t *fp) 271 { 272 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu; 273 274 if (fpu->fpu_flags & FPU_EN) { 275 if (!(fpu->fpu_flags & FPU_VALID)) { 276 /* 277 * FPU context is still active, release the 278 * ownership. 279 */ 280 fp_free(fpu, 0); 281 } 282 #if !defined(__amd64) 283 if (fp_kind == __FP_SSE) { 284 #endif 285 fpregset_to_fxsave(fp, &fpu->fpu_regs.kfpu_u.kfpu_fx); 286 fpu->fpu_regs.kfpu_xstatus = 287 fp->fp_reg_set.fpchip_state.xstatus; 288 #if !defined(__amd64) 289 } else 290 bcopy(fp, &fpu->fpu_regs.kfpu_u.kfpu_fn, 291 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn)); 292 #endif 293 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status; 294 fpu->fpu_flags |= FPU_VALID; 295 } else { 296 /* 297 * If we are trying to change the FPU state of a thread which 298 * hasn't yet initialized floating point, store the state in 299 * the pcb and indicate that the state is valid. When the 300 * thread enables floating point, it will use this state instead 301 * of the default state. 302 */ 303 #if !defined(__amd64) 304 if (fp_kind == __FP_SSE) { 305 #endif 306 fpregset_to_fxsave(fp, &fpu->fpu_regs.kfpu_u.kfpu_fx); 307 fpu->fpu_regs.kfpu_xstatus = 308 fp->fp_reg_set.fpchip_state.xstatus; 309 #if !defined(__amd64) 310 } else 311 bcopy(fp, &fpu->fpu_regs.kfpu_u.kfpu_fn, 312 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn)); 313 #endif 314 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status; 315 fpu->fpu_flags |= FPU_VALID; 316 } 317 } 318 319 /* 320 * Get floating-point registers into a native fpregset_t. 321 */ 322 void 323 getfpregs(klwp_t *lwp, fpregset_t *fp) 324 { 325 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu; 326 327 kpreempt_disable(); 328 if (fpu->fpu_flags & FPU_EN) { 329 /* 330 * If we have FPU hw and the thread's pcb doesn't have 331 * a valid FPU state then get the state from the hw. 332 */ 333 if (fpu_exists && ttolwp(curthread) == lwp && 334 !(fpu->fpu_flags & FPU_VALID)) 335 fp_save(fpu); /* get the current FPU state */ 336 } 337 338 /* 339 * There are 3 possible cases we have to be aware of here: 340 * 341 * 1. FPU is enabled. FPU state is stored in the current LWP. 342 * 343 * 2. FPU is not enabled, and there have been no intervening /proc 344 * modifications. Return initial FPU state. 345 * 346 * 3. FPU is not enabled, but a /proc consumer has modified FPU state. 347 * FPU state is stored in the current LWP. 348 */ 349 if ((fpu->fpu_flags & FPU_EN) || (fpu->fpu_flags & FPU_VALID)) { 350 /* 351 * Cases 1 and 3. 352 */ 353 #if !defined(__amd64) 354 if (fp_kind == __FP_SSE) { 355 #endif 356 fxsave_to_fpregset(&fpu->fpu_regs.kfpu_u.kfpu_fx, fp); 357 fp->fp_reg_set.fpchip_state.xstatus = 358 fpu->fpu_regs.kfpu_xstatus; 359 #if !defined(__amd64) 360 } else 361 bcopy(&fpu->fpu_regs.kfpu_u.kfpu_fn, fp, 362 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn)); 363 #endif 364 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status; 365 } else { 366 /* 367 * Case 2. 368 */ 369 #if !defined(__amd64) 370 if (fp_kind == __FP_SSE) { 371 #endif 372 fxsave_to_fpregset(&sse_initial, fp); 373 fp->fp_reg_set.fpchip_state.xstatus = 374 fpu->fpu_regs.kfpu_xstatus; 375 #if !defined(__amd64) 376 } else 377 bcopy(&x87_initial, fp, sizeof (x87_initial)); 378 #endif 379 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status; 380 } 381 kpreempt_enable(); 382 } 383 384 #if defined(_SYSCALL32_IMPL) 385 386 /* 387 * Set floating-point registers from an fpregset32_t. 388 */ 389 void 390 setfpregs32(klwp_t *lwp, fpregset32_t *fp) 391 { 392 fpregset_t fpregs; 393 394 fpregset_32ton(fp, &fpregs); 395 setfpregs(lwp, &fpregs); 396 } 397 398 /* 399 * Get floating-point registers into an fpregset32_t. 400 */ 401 void 402 getfpregs32(klwp_t *lwp, fpregset32_t *fp) 403 { 404 fpregset_t fpregs; 405 406 getfpregs(lwp, &fpregs); 407 fpregset_nto32(&fpregs, fp); 408 } 409 410 #endif /* _SYSCALL32_IMPL */ 411 412 /* 413 * Return the general registers 414 */ 415 void 416 getgregs(klwp_t *lwp, gregset_t grp) 417 { 418 struct regs *rp = lwptoregs(lwp); 419 #if defined(__amd64) 420 struct pcb *pcb = &lwp->lwp_pcb; 421 int thisthread = lwptot(lwp) == curthread; 422 423 grp[REG_RDI] = rp->r_rdi; 424 grp[REG_RSI] = rp->r_rsi; 425 grp[REG_RDX] = rp->r_rdx; 426 grp[REG_RCX] = rp->r_rcx; 427 grp[REG_R8] = rp->r_r8; 428 grp[REG_R9] = rp->r_r9; 429 grp[REG_RAX] = rp->r_rax; 430 grp[REG_RBX] = rp->r_rbx; 431 grp[REG_RBP] = rp->r_rbp; 432 grp[REG_R10] = rp->r_r10; 433 grp[REG_R11] = rp->r_r11; 434 grp[REG_R12] = rp->r_r12; 435 grp[REG_R13] = rp->r_r13; 436 grp[REG_R14] = rp->r_r14; 437 grp[REG_R15] = rp->r_r15; 438 grp[REG_FSBASE] = pcb->pcb_fsbase; 439 grp[REG_GSBASE] = pcb->pcb_gsbase; 440 if (thisthread) 441 kpreempt_disable(); 442 if (pcb->pcb_rupdate == 1) { 443 grp[REG_DS] = pcb->pcb_ds; 444 grp[REG_ES] = pcb->pcb_es; 445 grp[REG_FS] = pcb->pcb_fs; 446 grp[REG_GS] = pcb->pcb_gs; 447 } else { 448 grp[REG_DS] = rp->r_ds; 449 grp[REG_ES] = rp->r_es; 450 grp[REG_FS] = rp->r_fs; 451 grp[REG_GS] = rp->r_gs; 452 } 453 if (thisthread) 454 kpreempt_enable(); 455 grp[REG_TRAPNO] = rp->r_trapno; 456 grp[REG_ERR] = rp->r_err; 457 grp[REG_RIP] = rp->r_rip; 458 grp[REG_CS] = rp->r_cs; 459 grp[REG_SS] = rp->r_ss; 460 grp[REG_RFL] = rp->r_rfl; 461 grp[REG_RSP] = rp->r_rsp; 462 #else 463 bcopy(&rp->r_gs, grp, sizeof (gregset_t)); 464 #endif 465 } 466 467 #if defined(_SYSCALL32_IMPL) 468 469 void 470 getgregs32(klwp_t *lwp, gregset32_t grp) 471 { 472 struct regs *rp = lwptoregs(lwp); 473 struct pcb *pcb = &lwp->lwp_pcb; 474 int thisthread = lwptot(lwp) == curthread; 475 476 if (thisthread) 477 kpreempt_disable(); 478 if (pcb->pcb_rupdate == 1) { 479 grp[GS] = (uint16_t)pcb->pcb_gs; 480 grp[FS] = (uint16_t)pcb->pcb_fs; 481 grp[DS] = (uint16_t)pcb->pcb_ds; 482 grp[ES] = (uint16_t)pcb->pcb_es; 483 } else { 484 grp[GS] = (uint16_t)rp->r_gs; 485 grp[FS] = (uint16_t)rp->r_fs; 486 grp[DS] = (uint16_t)rp->r_ds; 487 grp[ES] = (uint16_t)rp->r_es; 488 } 489 if (thisthread) 490 kpreempt_enable(); 491 grp[EDI] = (greg32_t)rp->r_rdi; 492 grp[ESI] = (greg32_t)rp->r_rsi; 493 grp[EBP] = (greg32_t)rp->r_rbp; 494 grp[ESP] = 0; 495 grp[EBX] = (greg32_t)rp->r_rbx; 496 grp[EDX] = (greg32_t)rp->r_rdx; 497 grp[ECX] = (greg32_t)rp->r_rcx; 498 grp[EAX] = (greg32_t)rp->r_rax; 499 grp[TRAPNO] = (greg32_t)rp->r_trapno; 500 grp[ERR] = (greg32_t)rp->r_err; 501 grp[EIP] = (greg32_t)rp->r_rip; 502 grp[CS] = (uint16_t)rp->r_cs; 503 grp[EFL] = (greg32_t)rp->r_rfl; 504 grp[UESP] = (greg32_t)rp->r_rsp; 505 grp[SS] = (uint16_t)rp->r_ss; 506 } 507 508 void 509 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst) 510 { 511 mcontext_t *dmc = &dst->uc_mcontext; 512 const mcontext32_t *smc = &src->uc_mcontext; 513 514 bzero(dst, sizeof (*dst)); 515 dst->uc_flags = src->uc_flags; 516 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link; 517 518 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask)); 519 520 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp; 521 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size; 522 dst->uc_stack.ss_flags = src->uc_stack.ss_flags; 523 524 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS]; 525 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS]; 526 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES]; 527 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS]; 528 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI]; 529 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI]; 530 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP]; 531 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX]; 532 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX]; 533 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX]; 534 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX]; 535 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO]; 536 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR]; 537 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP]; 538 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS]; 539 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL]; 540 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP]; 541 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS]; 542 543 /* 544 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set 545 * otherwise there is no guarantee that anything in fpregs is valid. 546 */ 547 if (src->uc_flags & UC_FPU) 548 fpregset_32ton(&src->uc_mcontext.fpregs, 549 &dst->uc_mcontext.fpregs); 550 } 551 552 #endif /* _SYSCALL32_IMPL */ 553 554 /* 555 * Return the user-level PC. 556 * If in a system call, return the address of the syscall trap. 557 */ 558 greg_t 559 getuserpc() 560 { 561 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc; 562 uint32_t insn; 563 564 if (curthread->t_sysnum == 0) 565 return (upc); 566 567 /* 568 * We might've gotten here from sysenter (0xf 0x34), 569 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0). 570 * 571 * Go peek at the binary to figure it out.. 572 */ 573 if (fuword32((void *)(upc - 2), &insn) != -1 && 574 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f) 575 return (upc - 2); 576 return (upc - 7); 577 } 578 579 /* 580 * Protect segment registers from non-user privilege levels and GDT selectors 581 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment 582 * selector is non-null and not USER_CS/USER_DS, we make sure that the 583 * TI bit is set to point into the LDT and that the RPL is set to 3. 584 * 585 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we 586 * also explicitly zero the top 16 bits since they may be coming from the 587 * user's address space via setcontext(2) or /proc. 588 * 589 * Note about null selector. When running on the hypervisor if we allow a 590 * process to set its %cs to null selector with RPL of 0 the hypervisor will 591 * crash the domain. If running on bare metal we would get a #gp fault and 592 * be able to kill the process and continue on. Therefore we make sure to 593 * force RPL to SEL_UPL even for null selector when setting %cs. 594 */ 595 596 #if defined(IS_CS) || defined(IS_NOT_CS) 597 #error "IS_CS and IS_NOT_CS already defined" 598 #endif 599 600 #define IS_CS 1 601 #define IS_NOT_CS 0 602 603 /*ARGSUSED*/ 604 static greg_t 605 fix_segreg(greg_t sr, int iscs, model_t datamodel) 606 { 607 kthread_t *t = curthread; 608 609 switch (sr &= 0xffff) { 610 611 case 0: 612 if (iscs == IS_CS) 613 return (0 | SEL_UPL); 614 else 615 return (0); 616 617 #if defined(__amd64) 618 /* 619 * If lwp attempts to switch data model then force their 620 * code selector to be null selector. 621 */ 622 case U32CS_SEL: 623 if (datamodel == DATAMODEL_NATIVE) 624 return (0 | SEL_UPL); 625 else 626 return (sr); 627 628 case UCS_SEL: 629 if (datamodel == DATAMODEL_ILP32) 630 return (0 | SEL_UPL); 631 #elif defined(__i386) 632 case UCS_SEL: 633 #endif 634 /*FALLTHROUGH*/ 635 case UDS_SEL: 636 case LWPFS_SEL: 637 case LWPGS_SEL: 638 case SEL_UPL: 639 return (sr); 640 default: 641 break; 642 } 643 644 /* 645 * Allow this process's brand to do any necessary segment register 646 * manipulation. 647 */ 648 if (PROC_IS_BRANDED(t->t_procp) && BRMOP(t->t_procp)->b_fixsegreg) { 649 greg_t bsr = BRMOP(t->t_procp)->b_fixsegreg(sr, datamodel); 650 651 if (bsr == 0 && iscs == IS_CS) 652 return (0 | SEL_UPL); 653 else 654 return (bsr); 655 } 656 657 /* 658 * Force it into the LDT in ring 3 for 32-bit processes, which by 659 * default do not have an LDT, so that any attempt to use an invalid 660 * selector will reference the (non-existant) LDT, and cause a #gp 661 * fault for the process. 662 * 663 * 64-bit processes get the null gdt selector since they 664 * are not allowed to have a private LDT. 665 */ 666 #if defined(__amd64) 667 if (datamodel == DATAMODEL_ILP32) { 668 return (sr | SEL_TI_LDT | SEL_UPL); 669 } else { 670 if (iscs == IS_CS) 671 return (0 | SEL_UPL); 672 else 673 return (0); 674 } 675 676 #elif defined(__i386) 677 return (sr | SEL_TI_LDT | SEL_UPL); 678 #endif 679 } 680 681 /* 682 * Set general registers. 683 */ 684 void 685 setgregs(klwp_t *lwp, gregset_t grp) 686 { 687 struct regs *rp = lwptoregs(lwp); 688 model_t datamodel = lwp_getdatamodel(lwp); 689 690 #if defined(__amd64) 691 struct pcb *pcb = &lwp->lwp_pcb; 692 int thisthread = lwptot(lwp) == curthread; 693 694 if (datamodel == DATAMODEL_NATIVE) { 695 696 if (thisthread) 697 (void) save_syscall_args(); /* copy the args */ 698 699 rp->r_rdi = grp[REG_RDI]; 700 rp->r_rsi = grp[REG_RSI]; 701 rp->r_rdx = grp[REG_RDX]; 702 rp->r_rcx = grp[REG_RCX]; 703 rp->r_r8 = grp[REG_R8]; 704 rp->r_r9 = grp[REG_R9]; 705 rp->r_rax = grp[REG_RAX]; 706 rp->r_rbx = grp[REG_RBX]; 707 rp->r_rbp = grp[REG_RBP]; 708 rp->r_r10 = grp[REG_R10]; 709 rp->r_r11 = grp[REG_R11]; 710 rp->r_r12 = grp[REG_R12]; 711 rp->r_r13 = grp[REG_R13]; 712 rp->r_r14 = grp[REG_R14]; 713 rp->r_r15 = grp[REG_R15]; 714 rp->r_trapno = grp[REG_TRAPNO]; 715 rp->r_err = grp[REG_ERR]; 716 rp->r_rip = grp[REG_RIP]; 717 /* 718 * Setting %cs or %ss to anything else is quietly but 719 * quite definitely forbidden! 720 */ 721 rp->r_cs = UCS_SEL; 722 rp->r_ss = UDS_SEL; 723 rp->r_rsp = grp[REG_RSP]; 724 725 if (thisthread) 726 kpreempt_disable(); 727 728 pcb->pcb_ds = UDS_SEL; 729 pcb->pcb_es = UDS_SEL; 730 731 /* 732 * 64-bit processes -are- allowed to set their fsbase/gsbase 733 * values directly, but only if they're using the segment 734 * selectors that allow that semantic. 735 * 736 * (32-bit processes must use lwp_set_private().) 737 */ 738 pcb->pcb_fsbase = grp[REG_FSBASE]; 739 pcb->pcb_gsbase = grp[REG_GSBASE]; 740 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel); 741 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel); 742 743 /* 744 * Ensure that we go out via update_sregs 745 */ 746 pcb->pcb_rupdate = 1; 747 lwptot(lwp)->t_post_sys = 1; 748 if (thisthread) 749 kpreempt_enable(); 750 #if defined(_SYSCALL32_IMPL) 751 } else { 752 rp->r_rdi = (uint32_t)grp[REG_RDI]; 753 rp->r_rsi = (uint32_t)grp[REG_RSI]; 754 rp->r_rdx = (uint32_t)grp[REG_RDX]; 755 rp->r_rcx = (uint32_t)grp[REG_RCX]; 756 rp->r_rax = (uint32_t)grp[REG_RAX]; 757 rp->r_rbx = (uint32_t)grp[REG_RBX]; 758 rp->r_rbp = (uint32_t)grp[REG_RBP]; 759 rp->r_trapno = (uint32_t)grp[REG_TRAPNO]; 760 rp->r_err = (uint32_t)grp[REG_ERR]; 761 rp->r_rip = (uint32_t)grp[REG_RIP]; 762 763 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel); 764 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel); 765 766 rp->r_rsp = (uint32_t)grp[REG_RSP]; 767 768 if (thisthread) 769 kpreempt_disable(); 770 771 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel); 772 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel); 773 774 /* 775 * (See fsbase/gsbase commentary above) 776 */ 777 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel); 778 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel); 779 780 /* 781 * Ensure that we go out via update_sregs 782 */ 783 pcb->pcb_rupdate = 1; 784 lwptot(lwp)->t_post_sys = 1; 785 if (thisthread) 786 kpreempt_enable(); 787 #endif 788 } 789 790 /* 791 * Only certain bits of the flags register can be modified. 792 */ 793 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) | 794 (grp[REG_RFL] & PSL_USERMASK); 795 796 #elif defined(__i386) 797 798 /* 799 * Only certain bits of the flags register can be modified. 800 */ 801 grp[EFL] = (rp->r_efl & ~PSL_USERMASK) | (grp[EFL] & PSL_USERMASK); 802 803 /* 804 * Copy saved registers from user stack. 805 */ 806 bcopy(grp, &rp->r_gs, sizeof (gregset_t)); 807 808 rp->r_cs = fix_segreg(rp->r_cs, IS_CS, datamodel); 809 rp->r_ss = fix_segreg(rp->r_ss, IS_NOT_CS, datamodel); 810 rp->r_ds = fix_segreg(rp->r_ds, IS_NOT_CS, datamodel); 811 rp->r_es = fix_segreg(rp->r_es, IS_NOT_CS, datamodel); 812 rp->r_fs = fix_segreg(rp->r_fs, IS_NOT_CS, datamodel); 813 rp->r_gs = fix_segreg(rp->r_gs, IS_NOT_CS, datamodel); 814 815 #endif /* __i386 */ 816 } 817 818 /* 819 * Determine whether eip is likely to have an interrupt frame 820 * on the stack. We do this by comparing the address to the 821 * range of addresses spanned by several well-known routines. 822 */ 823 extern void _interrupt(); 824 extern void _allsyscalls(); 825 extern void _cmntrap(); 826 extern void fakesoftint(); 827 828 extern size_t _interrupt_size; 829 extern size_t _allsyscalls_size; 830 extern size_t _cmntrap_size; 831 extern size_t _fakesoftint_size; 832 833 /* 834 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking. 835 * Returns MIN(current stack depth, pcstack_limit). 836 */ 837 int 838 getpcstack(pc_t *pcstack, int pcstack_limit) 839 { 840 struct frame *fp = (struct frame *)getfp(); 841 struct frame *nextfp, *minfp, *stacktop; 842 int depth = 0; 843 int on_intr; 844 uintptr_t pc; 845 846 if ((on_intr = CPU_ON_INTR(CPU)) != 0) 847 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME)); 848 else 849 stacktop = (struct frame *)curthread->t_stk; 850 minfp = fp; 851 852 pc = ((struct regs *)fp)->r_pc; 853 854 while (depth < pcstack_limit) { 855 nextfp = (struct frame *)fp->fr_savfp; 856 pc = fp->fr_savpc; 857 if (nextfp <= minfp || nextfp >= stacktop) { 858 if (on_intr) { 859 /* 860 * Hop from interrupt stack to thread stack. 861 */ 862 stacktop = (struct frame *)curthread->t_stk; 863 minfp = (struct frame *)curthread->t_stkbase; 864 on_intr = 0; 865 continue; 866 } 867 break; 868 } 869 pcstack[depth++] = (pc_t)pc; 870 fp = nextfp; 871 minfp = fp; 872 } 873 return (depth); 874 } 875 876 /* 877 * The following ELF header fields are defined as processor-specific 878 * in the V8 ABI: 879 * 880 * e_ident[EI_DATA] encoding of the processor-specific 881 * data in the object file 882 * e_machine processor identification 883 * e_flags processor-specific flags associated 884 * with the file 885 */ 886 887 /* 888 * The value of at_flags reflects a platform's cpu module support. 889 * at_flags is used to check for allowing a binary to execute and 890 * is passed as the value of the AT_FLAGS auxiliary vector. 891 */ 892 int at_flags = 0; 893 894 /* 895 * Check the processor-specific fields of an ELF header. 896 * 897 * returns 1 if the fields are valid, 0 otherwise 898 */ 899 /*ARGSUSED2*/ 900 int 901 elfheadcheck( 902 unsigned char e_data, 903 Elf32_Half e_machine, 904 Elf32_Word e_flags) 905 { 906 if (e_data != ELFDATA2LSB) 907 return (0); 908 #if defined(__amd64) 909 if (e_machine == EM_AMD64) 910 return (1); 911 #endif 912 return (e_machine == EM_386); 913 } 914 915 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */ 916 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */ 917 #if defined(_SYSCALL32_IMPL) 918 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */ 919 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */ 920 #endif 921 922 /* 923 * Gather information about the processor and place it into auxv_hwcap 924 * so that it can be exported to the linker via the aux vector. 925 * 926 * We use this seemingly complicated mechanism so that we can ensure 927 * that /etc/system can be used to override what the system can or 928 * cannot discover for itself. 929 */ 930 void 931 bind_hwcap(void) 932 { 933 uint_t cpu_hwcap_flags = cpuid_pass4(NULL); 934 935 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags) & 936 ~auxv_hwcap_exclude; 937 938 #if defined(__amd64) 939 /* 940 * On AMD processors, sysenter just doesn't work at all 941 * when the kernel is in long mode. On IA-32e processors 942 * it does, but there's no real point in all the alternate 943 * mechanism when syscall works on both. 944 * 945 * Besides, the kernel's sysenter handler is expecting a 946 * 32-bit lwp ... 947 */ 948 auxv_hwcap &= ~AV_386_SEP; 949 #else 950 /* 951 * 32-bit processes can -always- use the lahf/sahf instructions 952 */ 953 auxv_hwcap |= AV_386_AHF; 954 #endif 955 956 if (auxv_hwcap_include || auxv_hwcap_exclude) 957 cmn_err(CE_CONT, "?user ABI extensions: %b\n", 958 auxv_hwcap, FMT_AV_386); 959 960 #if defined(_SYSCALL32_IMPL) 961 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags) & 962 ~auxv_hwcap32_exclude; 963 964 #if defined(__amd64) 965 /* 966 * If this is an amd64 architecture machine from Intel, then 967 * syscall -doesn't- work in compatibility mode, only sysenter does. 968 * 969 * Sigh. 970 */ 971 if (!cpuid_syscall32_insn(NULL)) 972 auxv_hwcap32 &= ~AV_386_AMD_SYSC; 973 974 /* 975 * 32-bit processes can -always- use the lahf/sahf instructions 976 */ 977 auxv_hwcap32 |= AV_386_AHF; 978 #endif 979 980 if (auxv_hwcap32_include || auxv_hwcap32_exclude) 981 cmn_err(CE_CONT, "?32-bit user ABI extensions: %b\n", 982 auxv_hwcap32, FMT_AV_386); 983 #endif 984 } 985 986 /* 987 * sync_icache() - this is called 988 * in proc/fs/prusrio.c. x86 has an unified cache and therefore 989 * this is a nop. 990 */ 991 /* ARGSUSED */ 992 void 993 sync_icache(caddr_t addr, uint_t len) 994 { 995 /* Do nothing for now */ 996 } 997 998 /*ARGSUSED*/ 999 void 1000 sync_data_memory(caddr_t va, size_t len) 1001 { 1002 /* Not implemented for this platform */ 1003 } 1004 1005 int 1006 __ipltospl(int ipl) 1007 { 1008 return (ipltospl(ipl)); 1009 } 1010 1011 /* 1012 * The panic code invokes panic_saveregs() to record the contents of a 1013 * regs structure into the specified panic_data structure for debuggers. 1014 */ 1015 void 1016 panic_saveregs(panic_data_t *pdp, struct regs *rp) 1017 { 1018 panic_nv_t *pnv = PANICNVGET(pdp); 1019 1020 struct cregs creg; 1021 1022 getcregs(&creg); 1023 1024 #if defined(__amd64) 1025 PANICNVADD(pnv, "rdi", rp->r_rdi); 1026 PANICNVADD(pnv, "rsi", rp->r_rsi); 1027 PANICNVADD(pnv, "rdx", rp->r_rdx); 1028 PANICNVADD(pnv, "rcx", rp->r_rcx); 1029 PANICNVADD(pnv, "r8", rp->r_r8); 1030 PANICNVADD(pnv, "r9", rp->r_r9); 1031 PANICNVADD(pnv, "rax", rp->r_rax); 1032 PANICNVADD(pnv, "rbx", rp->r_rbx); 1033 PANICNVADD(pnv, "rbp", rp->r_rbp); 1034 PANICNVADD(pnv, "r10", rp->r_r10); 1035 PANICNVADD(pnv, "r10", rp->r_r10); 1036 PANICNVADD(pnv, "r11", rp->r_r11); 1037 PANICNVADD(pnv, "r12", rp->r_r12); 1038 PANICNVADD(pnv, "r13", rp->r_r13); 1039 PANICNVADD(pnv, "r14", rp->r_r14); 1040 PANICNVADD(pnv, "r15", rp->r_r15); 1041 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE)); 1042 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE)); 1043 PANICNVADD(pnv, "ds", rp->r_ds); 1044 PANICNVADD(pnv, "es", rp->r_es); 1045 PANICNVADD(pnv, "fs", rp->r_fs); 1046 PANICNVADD(pnv, "gs", rp->r_gs); 1047 PANICNVADD(pnv, "trapno", rp->r_trapno); 1048 PANICNVADD(pnv, "err", rp->r_err); 1049 PANICNVADD(pnv, "rip", rp->r_rip); 1050 PANICNVADD(pnv, "cs", rp->r_cs); 1051 PANICNVADD(pnv, "rflags", rp->r_rfl); 1052 PANICNVADD(pnv, "rsp", rp->r_rsp); 1053 PANICNVADD(pnv, "ss", rp->r_ss); 1054 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3])); 1055 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0])); 1056 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3])); 1057 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0])); 1058 #elif defined(__i386) 1059 PANICNVADD(pnv, "gs", (uint32_t)rp->r_gs); 1060 PANICNVADD(pnv, "fs", (uint32_t)rp->r_fs); 1061 PANICNVADD(pnv, "es", (uint32_t)rp->r_es); 1062 PANICNVADD(pnv, "ds", (uint32_t)rp->r_ds); 1063 PANICNVADD(pnv, "edi", (uint32_t)rp->r_edi); 1064 PANICNVADD(pnv, "esi", (uint32_t)rp->r_esi); 1065 PANICNVADD(pnv, "ebp", (uint32_t)rp->r_ebp); 1066 PANICNVADD(pnv, "esp", (uint32_t)rp->r_esp); 1067 PANICNVADD(pnv, "ebx", (uint32_t)rp->r_ebx); 1068 PANICNVADD(pnv, "edx", (uint32_t)rp->r_edx); 1069 PANICNVADD(pnv, "ecx", (uint32_t)rp->r_ecx); 1070 PANICNVADD(pnv, "eax", (uint32_t)rp->r_eax); 1071 PANICNVADD(pnv, "trapno", (uint32_t)rp->r_trapno); 1072 PANICNVADD(pnv, "err", (uint32_t)rp->r_err); 1073 PANICNVADD(pnv, "eip", (uint32_t)rp->r_eip); 1074 PANICNVADD(pnv, "cs", (uint32_t)rp->r_cs); 1075 PANICNVADD(pnv, "eflags", (uint32_t)rp->r_efl); 1076 PANICNVADD(pnv, "uesp", (uint32_t)rp->r_uesp); 1077 PANICNVADD(pnv, "ss", (uint32_t)rp->r_ss); 1078 PANICNVADD(pnv, "gdt", creg.cr_gdt); 1079 PANICNVADD(pnv, "idt", creg.cr_idt); 1080 #endif /* __i386 */ 1081 1082 PANICNVADD(pnv, "ldt", creg.cr_ldt); 1083 PANICNVADD(pnv, "task", creg.cr_task); 1084 PANICNVADD(pnv, "cr0", creg.cr_cr0); 1085 PANICNVADD(pnv, "cr2", creg.cr_cr2); 1086 PANICNVADD(pnv, "cr3", creg.cr_cr3); 1087 if (creg.cr_cr4) 1088 PANICNVADD(pnv, "cr4", creg.cr_cr4); 1089 1090 PANICNVSET(pdp, pnv); 1091 } 1092 1093 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */ 1094 1095 #if !defined(__amd64) 1096 1097 /* 1098 * Given a return address (%eip), determine the likely number of arguments 1099 * that were pushed on the stack prior to its execution. We do this by 1100 * expecting that a typical call sequence consists of pushing arguments on 1101 * the stack, executing a call instruction, and then performing an add 1102 * on %esp to restore it to the value prior to pushing the arguments for 1103 * the call. We attempt to detect such an add, and divide the addend 1104 * by the size of a word to determine the number of pushed arguments. 1105 * 1106 * If we do not find such an add, we punt and return TR_ARG_MAX. It is not 1107 * possible to reliably determine if a function took no arguments (i.e. was 1108 * void) because assembler routines do not reliably perform an add on %esp 1109 * immediately upon returning (eg. _sys_call()), so returning TR_ARG_MAX is 1110 * safer than returning 0. 1111 */ 1112 static ulong_t 1113 argcount(uintptr_t eip) 1114 { 1115 const uint8_t *ins = (const uint8_t *)eip; 1116 ulong_t n; 1117 1118 enum { 1119 M_MODRM_ESP = 0xc4, /* Mod/RM byte indicates %esp */ 1120 M_ADD_IMM32 = 0x81, /* ADD imm32 to r/m32 */ 1121 M_ADD_IMM8 = 0x83 /* ADD imm8 to r/m32 */ 1122 }; 1123 1124 if (eip < KERNELBASE || ins[1] != M_MODRM_ESP) 1125 return (TR_ARG_MAX); 1126 1127 switch (ins[0]) { 1128 case M_ADD_IMM32: 1129 n = ins[2] + (ins[3] << 8) + (ins[4] << 16) + (ins[5] << 24); 1130 break; 1131 1132 case M_ADD_IMM8: 1133 n = ins[2]; 1134 break; 1135 1136 default: 1137 return (TR_ARG_MAX); 1138 } 1139 1140 n /= sizeof (long); 1141 return (MIN(n, TR_ARG_MAX)); 1142 } 1143 1144 #endif /* !__amd64 */ 1145 1146 /* 1147 * Print a stack backtrace using the specified frame pointer. We delay two 1148 * seconds before continuing, unless this is the panic traceback. Note 1149 * that the frame for the starting stack pointer value is omitted because 1150 * the corresponding %eip is not known. 1151 */ 1152 #if defined(__amd64) 1153 1154 void 1155 traceback(caddr_t fpreg) 1156 { 1157 struct frame *fp = (struct frame *)fpreg; 1158 struct frame *nextfp; 1159 uintptr_t pc, nextpc; 1160 ulong_t off; 1161 char args[TR_ARG_MAX * 2 + 16], *sym; 1162 1163 if (!panicstr) 1164 printf("traceback: %%fp = %p\n", (void *)fp); 1165 1166 fp = (struct frame *)plat_traceback(fpreg); 1167 if ((uintptr_t)fp < KERNELBASE) 1168 goto out; 1169 1170 pc = fp->fr_savpc; 1171 fp = (struct frame *)fp->fr_savfp; 1172 1173 while ((uintptr_t)fp >= KERNELBASE) { 1174 /* 1175 * XX64 Until port is complete tolerate 8-byte aligned 1176 * frame pointers but flag with a warning so they can 1177 * be fixed. 1178 */ 1179 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) { 1180 if (((uintptr_t)fp & (8 - 1)) == 0) { 1181 printf(" >> warning! 8-byte" 1182 " aligned %%fp = %p\n", (void *)fp); 1183 } else { 1184 printf( 1185 " >> mis-aligned %%fp = %p\n", (void *)fp); 1186 break; 1187 } 1188 } 1189 1190 args[0] = '\0'; 1191 nextpc = (uintptr_t)fp->fr_savpc; 1192 nextfp = (struct frame *)fp->fr_savfp; 1193 if ((sym = kobj_getsymname(pc, &off)) != NULL) { 1194 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp, 1195 mod_containing_pc((caddr_t)pc), sym, off, args); 1196 } else { 1197 printf("%016lx %lx (%s)\n", 1198 (uintptr_t)fp, pc, args); 1199 } 1200 1201 pc = nextpc; 1202 fp = nextfp; 1203 } 1204 out: 1205 if (!panicstr) { 1206 printf("end of traceback\n"); 1207 DELAY(2 * MICROSEC); 1208 } 1209 } 1210 1211 #elif defined(__i386) 1212 1213 void 1214 traceback(caddr_t fpreg) 1215 { 1216 struct frame *fp = (struct frame *)fpreg; 1217 struct frame *nextfp, *minfp, *stacktop; 1218 uintptr_t pc, nextpc; 1219 1220 cpu_t *cpu; 1221 1222 /* 1223 * args[] holds TR_ARG_MAX hex long args, plus ", " or '\0'. 1224 */ 1225 char args[TR_ARG_MAX * 2 + 8], *p; 1226 1227 int on_intr; 1228 ulong_t off; 1229 char *sym; 1230 1231 if (!panicstr) 1232 printf("traceback: %%fp = %p\n", (void *)fp); 1233 1234 /* 1235 * If we are panicking, all high-level interrupt information in 1236 * CPU was overwritten. panic_cpu has the correct values. 1237 */ 1238 kpreempt_disable(); /* prevent migration */ 1239 1240 cpu = (panicstr && CPU->cpu_id == panic_cpu.cpu_id)? &panic_cpu : CPU; 1241 1242 if ((on_intr = CPU_ON_INTR(cpu)) != 0) 1243 stacktop = (struct frame *)(cpu->cpu_intr_stack + SA(MINFRAME)); 1244 else 1245 stacktop = (struct frame *)curthread->t_stk; 1246 1247 kpreempt_enable(); 1248 1249 fp = (struct frame *)plat_traceback(fpreg); 1250 if ((uintptr_t)fp < KERNELBASE) 1251 goto out; 1252 1253 minfp = fp; /* Baseline minimum frame pointer */ 1254 pc = fp->fr_savpc; 1255 fp = (struct frame *)fp->fr_savfp; 1256 1257 while ((uintptr_t)fp >= KERNELBASE) { 1258 ulong_t argc; 1259 long *argv; 1260 1261 if (fp <= minfp || fp >= stacktop) { 1262 if (on_intr) { 1263 /* 1264 * Hop from interrupt stack to thread stack. 1265 */ 1266 stacktop = (struct frame *)curthread->t_stk; 1267 minfp = (struct frame *)curthread->t_stkbase; 1268 on_intr = 0; 1269 continue; 1270 } 1271 break; /* we're outside of the expected range */ 1272 } 1273 1274 if ((uintptr_t)fp & (STACK_ALIGN - 1)) { 1275 printf(" >> mis-aligned %%fp = %p\n", (void *)fp); 1276 break; 1277 } 1278 1279 nextpc = fp->fr_savpc; 1280 nextfp = (struct frame *)fp->fr_savfp; 1281 argc = argcount(nextpc); 1282 argv = (long *)((char *)fp + sizeof (struct frame)); 1283 1284 args[0] = '\0'; 1285 p = args; 1286 while (argc-- > 0 && argv < (long *)stacktop) { 1287 p += snprintf(p, args + sizeof (args) - p, 1288 "%s%lx", (p == args) ? "" : ", ", *argv++); 1289 } 1290 1291 if ((sym = kobj_getsymname(pc, &off)) != NULL) { 1292 printf("%08lx %s:%s+%lx (%s)\n", (uintptr_t)fp, 1293 mod_containing_pc((caddr_t)pc), sym, off, args); 1294 } else { 1295 printf("%08lx %lx (%s)\n", 1296 (uintptr_t)fp, pc, args); 1297 } 1298 1299 minfp = fp; 1300 pc = nextpc; 1301 fp = nextfp; 1302 } 1303 out: 1304 if (!panicstr) { 1305 printf("end of traceback\n"); 1306 DELAY(2 * MICROSEC); 1307 } 1308 } 1309 1310 #endif /* __i386 */ 1311 1312 /* 1313 * Generate a stack backtrace from a saved register set. 1314 */ 1315 void 1316 traceregs(struct regs *rp) 1317 { 1318 traceback((caddr_t)rp->r_fp); 1319 } 1320 1321 void 1322 exec_set_sp(size_t stksize) 1323 { 1324 klwp_t *lwp = ttolwp(curthread); 1325 1326 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize; 1327 } 1328 1329 hrtime_t 1330 gethrtime_waitfree(void) 1331 { 1332 return (dtrace_gethrtime()); 1333 } 1334 1335 hrtime_t 1336 gethrtime(void) 1337 { 1338 return (gethrtimef()); 1339 } 1340 1341 hrtime_t 1342 gethrtime_unscaled(void) 1343 { 1344 return (gethrtimeunscaledf()); 1345 } 1346 1347 void 1348 scalehrtime(hrtime_t *hrt) 1349 { 1350 scalehrtimef(hrt); 1351 } 1352 1353 uint64_t 1354 unscalehrtime(hrtime_t nsecs) 1355 { 1356 return (unscalehrtimef(nsecs)); 1357 } 1358 1359 void 1360 gethrestime(timespec_t *tp) 1361 { 1362 gethrestimef(tp); 1363 } 1364 1365 #if defined(__amd64) 1366 /* 1367 * Part of the implementation of hres_tick(); this routine is 1368 * easier in C than assembler .. called with the hres_lock held. 1369 * 1370 * XX64 Many of these timekeeping variables need to be extern'ed in a header 1371 */ 1372 1373 #include <sys/time.h> 1374 #include <sys/machlock.h> 1375 1376 extern int one_sec; 1377 extern int max_hres_adj; 1378 1379 void 1380 __adj_hrestime(void) 1381 { 1382 long long adj; 1383 1384 if (hrestime_adj == 0) 1385 adj = 0; 1386 else if (hrestime_adj > 0) { 1387 if (hrestime_adj < max_hres_adj) 1388 adj = hrestime_adj; 1389 else 1390 adj = max_hres_adj; 1391 } else { 1392 if (hrestime_adj < -max_hres_adj) 1393 adj = -max_hres_adj; 1394 else 1395 adj = hrestime_adj; 1396 } 1397 1398 timedelta -= adj; 1399 hrestime_adj = timedelta; 1400 hrestime.tv_nsec += adj; 1401 1402 while (hrestime.tv_nsec >= NANOSEC) { 1403 one_sec++; 1404 hrestime.tv_sec++; 1405 hrestime.tv_nsec -= NANOSEC; 1406 } 1407 } 1408 #endif 1409 1410 /* 1411 * Wrapper functions to maintain backwards compability 1412 */ 1413 int 1414 xcopyin(const void *uaddr, void *kaddr, size_t count) 1415 { 1416 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED)); 1417 } 1418 1419 int 1420 xcopyout(const void *kaddr, void *uaddr, size_t count) 1421 { 1422 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED)); 1423 } 1424
Indexes created Sat Nov 21 22:21:38 UTC 2009
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