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      1 /*
      2  * CDDL HEADER START
      3  *
      4  * The contents of this file are subject to the terms of the
      5  * Common Development and Distribution License, Version 1.0 only
      6  * (the "License").  You may not use this file except in compliance
      7  * with the License.
      8  *
      9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
     10  * or http://www.opensolaris.org/os/licensing.
     11  * See the License for the specific language governing permissions
     12  * and limitations under the License.
     13  *
     14  * When distributing Covered Code, include this CDDL HEADER in each
     15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
     16  * If applicable, add the following below this CDDL HEADER, with the
     17  * fields enclosed by brackets "[]" replaced with your own identifying
     18  * information: Portions Copyright [yyyy] [name of copyright owner]
     19  *
     20  * CDDL HEADER END
     21  */
     22 /*
     23  * Copyright (c) 1986 by Sun Microsystems, Inc.
     24  */
     25 
     26 #ifndef _SYS_FSR_H
     27 #define	_SYS_FSR_H
     28 
     29 #pragma ident	"%Z%%M%	%I%	%E% SMI" /* from SunOS psl.h 1.2 */
     30 
     31 #ifdef	__cplusplus
     32 extern "C" {
     33 #endif
     34 
     35 
     36 /*
     37  * Floating Point State Register (FSR)
     38  *
     39  * Notes:
     40  *	On v9 cpus, the fsr is 64b.
     41  *	On v7 and v8 cpus, it is 32b.
     42  *
     43  *	FCC1 thru FCC3 are v9 only.
     44  *	RP is v7 only (v8 dropped extended precision).
     45  *	PR was dropped before v7.
     46  *
     47  *   |------------------------------------------------------------------------|
     48  *   |				---			 | FCC3 | FCC2 | FCC1 |
     49  *   |---------------------------------------------------|------|------|------|
     50  *    63						38 37  36 35  34 33  32
     51  *
     52  *   |------------------------------------------------------------------------|
     53  *   |  RD |  RP | TEM | NS | --- | VER | FTT | QNE | PR | FCC0 | AEXC | CEXC |
     54  *   |-----|-----|-----|----|-----|-----|-----|-----|----|------|------|------|
     55  *    31 30 29 28 27 23  22  21 20 19 17 16 14  13    12  11  10 9    5 4    0
     56  */
     57 #define	FSR_CEXC	0x0000001f	/* Current Exception */
     58 #define	FSR_AEXC	0x000003e0	/* ieee accrued exceptions */
     59 #define	FSR_FCC		0x00000c00	/* Floating-point Condition Codes */
     60 #define	FSR_PR		0x00001000	/* Partial Remainder */
     61 #define	FSR_QNE		0x00002000	/* Queue not empty */
     62 #define	FSR_FTT		0x0001c000	/* Floating-point Trap Type */
     63 #define	FSR_VER		0x000e0000	/* fpu version */
     64 #define	FSR_TEM		0x0f800000	/* ieee Trap Enable Mask */
     65 #define	FSR_RP		0x30000000	/* Rounding Precision */
     66 #define	FSR_RD		0xc0000000	/* Rounding Direction */
     67 #define	FSR_VER_SHIFT	17		/* version shift */
     68 #define	FSR_FCC1	0x00000003	/* fp condition codes set #1 */
     69 #define	FSR_FCC2	0x0000000C	/* fp condition codes set #2 */
     70 #define	FSR_FCC3	0x00000030	/* fp condition codes set #3 */
     71 
     72 /*
     73  * Definition of CEXC (Current EXCeption) bit field of fsr
     74  */
     75 #define	FSR_CEXC_NX	0x00000001	/* inexact */
     76 #define	FSR_CEXC_DZ	0x00000002	/* divide-by-zero */
     77 #define	FSR_CEXC_UF	0x00000004	/* underflow */
     78 #define	FSR_CEXC_OF	0x00000008	/* overflow */
     79 #define	FSR_CEXC_NV	0x00000010	/* invalid */
     80 
     81 /*
     82  * Definition of AEXC (Accrued EXCeption) bit field of fsr
     83  */
     84 #define	FSR_AEXC_NX	(0x1 << 5)	/* inexact */
     85 #define	FSR_AEXC_DZ	(0x2 << 5)	/* divide-by-zero */
     86 #define	FSR_AEXC_UF	(0x4 << 5)	/* underflow */
     87 #define	FSR_AEXC_OF	(0x8 << 5)	/* overflow */
     88 #define	FSR_AEXC_NV	(0x10 << 5)	/* invalid */
     89 
     90 /*
     91  * Definition of FTT (Floating-point Trap Type) field within the FSR
     92  */
     93 #define	FTT_NONE	0		/* no exceptions */
     94 #define	FTT_IEEE	1		/* IEEE exception */
     95 #define	FTT_UNFIN	2		/* unfinished fpop */
     96 #define	FTT_UNIMP	3		/* unimplemented fpop */
     97 #define	FTT_SEQ		4		/* sequence error */
     98 #define	FTT_ALIGN	5	/* alignment, by software convention */
     99 #define	FTT_DFAULT	6	/* data fault, by software convention */
    100 #define	FSR_FTT_SHIFT	14	/* shift needed to justify ftt field */
    101 #define	FSR_FTT_IEEE	(FTT_IEEE   << FSR_FTT_SHIFT)
    102 #define	FSR_FTT_UNFIN	(FTT_UNFIN  << FSR_FTT_SHIFT)
    103 #define	FSR_FTT_UNIMP	(FTT_UNIMP  << FSR_FTT_SHIFT)
    104 #define	FSR_FTT_SEQ	(FTT_SEQ    << FSR_FTT_SHIFT)
    105 #define	FSR_FTT_ALIGN	(FTT_ALIGN  << FSR_FTT_SHIFT)
    106 #define	FSR_FTT_DFAULT	(FTT_DFAULT << FSR_FTT_SHIFT)
    107 
    108 /*
    109  * Definition of TEM (Trap Enable Mask) bit field of fsr
    110  */
    111 #define	FSR_TEM_NX	(0x1 << 23)	/* inexact */
    112 #define	FSR_TEM_DZ	(0x2 << 23)	/* divide-by-zero */
    113 #define	FSR_TEM_UF	(0x4 << 23)	/* underflow */
    114 #define	FSR_TEM_OF	(0x8 << 23)	/* overflow */
    115 #define	FSR_TEM_NV	(0x10 << 23)	/* invalid */
    116 
    117 /*
    118  * Definition of RP (Rounding Precision) field of fsr
    119  */
    120 #define	RP_DBLEXT	0		/* double-extended */
    121 #define	RP_SINGLE	1		/* single */
    122 #define	RP_DOUBLE	2		/* double */
    123 #define	RP_RESERVED	3		/* unused and reserved */
    124 
    125 /*
    126  * Definition of RD (Rounding Direction) field of fsr
    127  */
    128 #define	RD_NEAR		0		/* nearest or even if tie */
    129 #define	RD_ZER0		1		/* to zero */
    130 #define	RD_POSINF	2		/* positive infinity */
    131 #define	RD_NEGINF	3		/* negative infinity */
    132 
    133 
    134 /*
    135  * Floating Point Registers State (FPRS)
    136  *	(For V9 only)
    137  *
    138  *   |---------------|
    139  *   | FEF | DU | DL |
    140  *   |-----|----|----|
    141  *      2    1     0
    142  */
    143 #define	FPRS_DL		0x1	/* dirty lower */
    144 #define	FPRS_DU		0x2	/* dirty upper */
    145 #define	FPRS_FEF	0x4	/* enable fp */
    146 
    147 #ifdef	__cplusplus
    148 }
    149 #endif
    150 
    151 #endif	/* _SYS_FSR_H */
    152